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91. 发明授权

US5844718A Image processing apparatus and method in which multi-level color signal with removed edge component is encoded 失效
标题翻译：具有去除边缘分量的多级彩色信号被编码的图像处理装置和方法
公开(公告)号：US5844718A
公开(公告)日：1998-12-01
申请号：US285523
申请日：1994-08-04
申请人： Hidefumi Ohsawa , Yasuji Hirabayashi , Tadashi Yoshida
发明人： Hidefumi Ohsawa , Yasuji Hirabayashi , Tadashi Yoshida
IPC分类号： G06T9/00 , H03M7/12 , H04N1/41 , H04N1/64 , H04N7/26
CPC分类号： H04N1/642 , H03M7/12 , H04N19/30
摘要： An image processing apparatus in which a multi-level color signal is input and converted into a binary color signal. An edge component is removed from the multi-level color signal based on the binary color signal and the binary color signal and the multi-level color signal of which the edge component is removed are encoded.
摘要翻译：一种图像处理装置，其中多级彩色信号被输入并转换为二进制彩色信号。基于二进制颜色信号和二进制彩色信号以及去除边缘分量的多级彩色信号对多级彩色信号中的边缘分量进行编码。

92. 发明授权

US5146422A Reduced execution time convert to binary circuit 失效
标题翻译：减少执行时间转换为二进制电路
公开(公告)号：US5146422A
公开(公告)日：1992-09-08
申请号：US722588
申请日：1991-06-27
申请人： Klaus K. Maass , David T. Shen
发明人： Klaus K. Maass , David T. Shen
IPC分类号： F02B75/02 , G06F7/48 , G06F7/52 , G06F7/535 , H03M7/12
CPC分类号： G06F7/535 , G06F7/491 , G06F7/5375 , H03M7/12 , F02B2075/027
摘要： An apparatus for converting a multidigit decimal number into a binary number. In a preferred embodiment, the apparatus includes a register for holding the multidigit decimal number; first conversion logic, coupled to the register, for simultaneously converting a first pair of decimal digits in the multidigit decimal number, into a first binary representation and second conversion logic, coupled to said first conversion logic and the register, for simultaneously converting a second pair of decimal digits in the multidigit decimal number and the first binary representation into a second binary representation of a decimal number defined by the first and second pair of decimal digits.
摘要翻译：用于将多位十进制数转换为二进制数的装置。在优选实施例中，该装置包括用于保存多位十进制数的寄存器; 第一转换逻辑，耦合到寄存器，用于同时将多位十进制数中的第一对十进制数字转换为耦合到所述第一转换逻辑和寄存器的第一二进制表示和第二转换逻辑，用于同时转换第二对十进制十进制数字中的十进制数字，第一个二进制表示形式转换成由第一和第二对十进制数字定义的十进制数的第二个二进制表示形式。

93. 发明授权

US5132925A Radix-16 divider using overlapped quotient bit selection and concurrent quotient rounding and correction 失效
标题翻译： Radix-16分频器使用重叠商位选择和并发商舍入和校正
公开(公告)号：US5132925A
公开(公告)日：1992-07-21
申请号：US602721
申请日：1990-10-24
申请人： Theodore H. Kehl , David N. Cutler
发明人： Theodore H. Kehl , David N. Cutler
IPC分类号： G06F7/52 , H03M7/12
CPC分类号： H03M7/12 , G06F7/535 , G06F7/5375 , G06F2207/3844 , G06F7/49963
摘要： A radix-16 divider, generally including two improved radix-4 dividers cascaded combinatorially, also utilizes improved overlapping quotient bit selection, together with concurrent quotient bit selection and rounding techniques, to produce four bits of quotient per divider cycle with reduced hardware requirements.
摘要翻译：通常包括组合级联的两个改进的基数-4分频器的基数16分频器还利用改进的重叠商位选择以及并发商位选择和舍入技术，以减少硬件要求在每个分频器周期产生四位商。

94. 发明授权

US4638300A Central processing unit having built-in BCD operation 失效
标题翻译：中央处理单元内置BCD操作
公开(公告)号：US4638300A
公开(公告)日：1987-01-20
申请号：US376317
申请日：1982-05-10
申请人： Michael J. Miller
发明人： Michael J. Miller
IPC分类号： G06F7/494 , G06F7/50 , H03M7/12
CPC分类号： G06F7/494 , H03M7/12 , G06F2207/4921 , G06F2207/4924
摘要： A CPU data path portion having an ALU, an adjuster unit, a shifter unit and a shift register unit is disclosed. The CPU is capable of selectively forming the sum or difference of a first BCD operand and a second BCD operand by arithmetically combining the operands with the ALU to form binary results, the results dependent upon the arithmetic operation selected and adjusting the results with the adjuster unit into BCD, the adjustment also dependent upon the arithmetic operation selected. The CPU is further capable of selectively converting an operand from binary to BCD format or from BCD to binary format by iteratively shifting the operand between the shifter unit and the shift register unit and correcting the operand with the ALU, the direction of the shift and the ALU correction dependent upon the conversion selected.
摘要翻译：公开了具有ALU，调整单元，移位单元和移位寄存器单元的CPU数据路径部分。 CPU能够通过将操作数与ALU进行算术组合来选择性地形成第一BCD操作数和第二BCD操作数的差值，以形成二进制结果，结果取决于所选择的算术运算，并用调整单元调整结果进入BCD，调整也取决于所选择的算术运算。 CPU还能够通过迭代地移位移位器单元和移位寄存器单元之间的操作数并且用ALU，移位方向和移位寄存器单元来校正操作数，从而将操作数从BCD格式或BCD格式转换成二进制格式 ALU校正取决于所选择的转换。

95. 发明授权

US4325056A BCD To binary converter 失效
标题翻译： BCD到二进制转换器
公开(公告)号：US4325056A
公开(公告)日：1982-04-13
申请号：US180255
申请日：1980-08-22
申请人： Daniel P. Wiener
发明人： Daniel P. Wiener
IPC分类号： H03M7/12 , G06F5/02 , H03K13/24
CPC分类号： H03M7/12
摘要： A BCD to binary converter, particularly applicable for large numbers, employing an input level of code converter logic comprising PROM groups which provide a specially chosen initial conversion of the BCD number to be converted. Each PROM group comprises a plurality of individually programmed PROMs which provide for this initial conversion by directly converting successive sequential pairs of BCD digits into equivalent binary numbers taking into account their order of significance. A binary adder employing a plurality of PROM logic levels then provides for the binary addition of the binary bits produced by this initial conversion to provide the desired overall BCD to binary conversion.
摘要翻译：一种BCD到二进制转换器，特别适用于大数量，采用包括PROM组的代码转换器逻辑的输入电平，其提供要转换的BCD数字的特别选择的初始转换。每个PROM组包括多个单独编程的PROM，其通过将BCD数字的连续顺序对直接转换为等效二进制数来提供该初始转换，同时考虑其重要性的顺序。采用多个PROM逻辑电平的二进制加法器然后提供由该初始转换产生的二进制位的二进制相加，以提供期望的总体BCD到二进制转换。

96. 发明授权

US3715574A Interface converter for feeding high frequency signals into low frequency circuits 失效
标题翻译：用于将高频信号馈入低频电路的接口转换器
公开(公告)号：US3715574A
公开(公告)日：1973-02-06
申请号：US3715574D
申请日：1971-07-21
申请人： US NAVY
发明人： GOWAN R
IPC分类号： H03M7/12 , G06F5/02 , G06F5/06 , H04L3/00
CPC分类号： H03M7/12
摘要： Apparatus for conversion of high speed binary to binary coded decimal with low speed circuitry. An information incoming pulse is digitized at the high frequency rate and this digital equivalent is stored in a first bit register. A low frequency digitizing oscillator is coupled through a gate circuit to a bit register identical to the first bit register and into a binaryto-digital converter. A bit by bit comparator compares the high frequency pulse count with the low frequency pulse count and produces a stop signal to the gate circuit when the low frequency count equals the stored high frequency count.
摘要翻译：用低速电路将高速二进制转换为二进制编码十进制的装置。信息输入脉冲以高频率数字化，该数字等效存储在第一位寄存器中。低频数字化振荡器通过栅极电路耦合到与第一位寄存器相同的位寄存器并转换成二进制到数字转换器。逐位比较器将高频脉冲计数与低频脉冲计数进行比较，当低频计数等于存储的高频计数时，产生停止信号给门电路。

97. 发明授权

US3649823A Digital translator 失效
标题翻译：数字翻译
公开(公告)号：US3649823A
公开(公告)日：1972-03-14
申请号：US3649823D
申请日：1969-12-22
申请人： ADTROL ELECTRONICS INC
发明人： BUSCH EDWARD G
IPC分类号： H03M7/12 , H04L3/00
CPC分类号： H03M7/12
摘要： A translator for converting a weighted binary-coded signal representative of a number into a decimal representation of the number. The translator includes means for receiving a binarycoded signal, a source of clock pulses and a replaceable unit having both gating means which is comprised of a plurality of coincidence gates and a counting means which is comprised of a plurality of decimal counters. Each of the counters corresponds to a digit of the decimal number generated by the translator. The unit further includes a plurality of conductive leads which are responsive to the binary signal and the clock pulses. The gates are connectable to the conductive leads in accordance with the decimal significance of each bit of the binary code so that the gating means enable the passage of clock pulses to the counter in accordance with the decimal significance of each bit of the binary signal which is present. The counter is stepped to the count corresponding to the number. Display means are provided which are responsive to the counter for visually displaying the number.
摘要翻译：一个转换器，用于将表示数字的加权二进制编码信号转换为数字的十进制表示。翻译器包括用于接收二进制编码信号，时钟脉冲源的装置和具有由多个符合门组成的门控装置的可替换单元和由多个十进制计数器组成的计数装置。每个计数器对应于由翻译器生成的十进制数字的数字。该单元还包括响应二进制信号和时钟脉冲的多个导电引线。根据二进制代码的每个位的十进制值，门可以连接到导线，使得门控装置能够根据二进制信号的每个位的十进制值来计数到计数器当下。计数器被加到与数字对应的计数。提供了显示装置，其响应于计数器来可视地显示该数量。

98. 发明授权

US3535497A Bcd to decimal decoder 失效
标题翻译： BCD到DECIMAL DECODER
公开(公告)号：US3535497A
公开(公告)日：1970-10-20
申请号：US3535497D
申请日：1967-06-21
申请人： NASA
发明人： BYRNE FRANK
IPC分类号： H03M7/12 , H03K13/24 , H03K13/243
CPC分类号： H03M7/12

99. 发明授权

US3524976A Binary coded decimal to binary conversion 失效
标题翻译：二进制代码转换为二进制转换
公开(公告)号：US3524976A
公开(公告)日：1970-08-18
申请号：US3524976D
申请日：1965-04-21
申请人： RCA CORP
发明人： WANG MAO CHANG
IPC分类号： H03M7/12 , G06F5/00
CPC分类号： H03M7/12

100. 发明授权

US3242323A Binary to decimal binary code translator 失效
标题翻译：二进制到十进制二进制代码转换器
公开(公告)号：US3242323A
公开(公告)日：1966-03-22
申请号：US24324462
申请日：1962-12-10
申请人： WESTINGHOUSE AIR BRAKE CO
发明人： MARASCO RUSSELL J
IPC分类号： H03M7/12
CPC分类号： H03M7/12

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