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91. 发明申请

US20080164498A1 FORMING A SEMICONDUCTOR DEVICE HAVING A METAL ELECTRODE AND STRUCTURE THEREOF 有权
标题翻译：形成具有金属电极的半导体器件及其结构
公开(公告)号：US20080164498A1
公开(公告)日：2008-07-10
申请号：US11619861
申请日：2007-01-04
申请人： William J. Taylor
发明人： William J. Taylor
IPC分类号： H01L29/423 , H01L21/04 , H01L21/71
CPC分类号： H01L29/66545 , H01L21/28026 , H01L29/49 , H01L29/665 , H01L29/6659
摘要： A method for forming a semiconductor device includes forming a gate dielectric over a substrate, forming a metal electrode over the gate dielectric, forming a first sacrificial layer which includes polysilicon or a metal over the metal electrode, removing the first sacrificial layer, and forming a gate electrode contact over and coupled to the metal electrode.
摘要翻译：一种用于形成半导体器件的方法包括在衬底上形成栅极电介质，在栅极电介质上形成金属电极，在金属电极上形成包括多晶硅或金属的第一牺牲层，去除第一牺牲层，并形成栅电极接触并耦合到金属电极。

92. 发明申请

US20080083964A1 Semiconductor image sensor die and production method thereof, semiconductor image sensor module, image sensor device, optical device element, and optical device module 审中-公开
标题翻译：半导体图像传感器芯片及其制造方法，半导体图像传感器模块，图像传感器装置，光学元件元件和光学器件模块
公开(公告)号：US20080083964A1
公开(公告)日：2008-04-10
申请号：US11889675
申请日：2007-08-15
申请人： Hiroaki Fujimoto , Masanori Minamio , Toshiyuki Fukuda
发明人： Hiroaki Fujimoto , Masanori Minamio , Toshiyuki Fukuda
IPC分类号： H01L31/0232 , H01L21/71
CPC分类号： H01L27/14618 , H01L27/14625 , H01L31/0203 , H01L31/0232 , H01L2224/45124 , H01L2224/45144 , H01L2224/48465 , H01L2924/10252 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/1033 , H01L2924/10335 , H01L2924/3025 , H01L2224/48091 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor image sensor die includes a substrate, an imaging area, a surrounding circuit area, a plurality of electrode portions, a translucent member, a transparent adhesive, and a bump. The imaging area, the surrounding circuit area, and the electrode portion are provided on an upper surface of the substrate. The surrounding circuit area is provided outside the imaging area. The electrode portion is provided outside the surrounding circuit area. The translucent member is adhered via the transparent adhesive to the imaging area, covering the imaging area. The bump is provided on a portion of the electrode portions. The surface of the bump includes an upper surface which is located higher than an upper surface of the transparent adhesive.
摘要翻译：半导体图像传感器芯片包括基板，成像区域，周围电路区域，多个电极部分，半透明构件，透明粘合剂和凸块。成像区域，周围电路区域和电极部分设置在基板的上表面上。周围的电路区域设置在成像区域的外部。电极部设置在周围电路区域的外侧。半透明构件通过透明粘合剂粘附到成像区域，覆盖成像区域。凸块设置在电极部分的一部分上。凸起的表面包括位于比透明粘合剂的上表面高的上表面。

93. 发明申请

US20080020518A1 LIQUID CRYSTAL DISPLAY PANEL 失效
标题翻译：液晶显示面板
公开(公告)号：US20080020518A1
公开(公告)日：2008-01-24
申请号：US11782042
申请日：2007-07-24
申请人： Hongyong Zhang , Satoshi Teramoto
发明人： Hongyong Zhang , Satoshi Teramoto
IPC分类号： H01L21/71
CPC分类号： G02F1/13392 , G02F1/1334 , G02F1/1339 , G02F1/1341 , G02F1/13454 , G02F2001/133388 , G09G3/3648
摘要： A laminated spacer portion formed by laminating various thin films that constitute thin-film transistors is disposed in peripheral driver circuits. As a result, even in a structure in which part of a sealing member is disposed above the peripheral driver circuits, pressure exerted from spacers in the sealing member is concentrated on the laminated spacer portion, whereby destruction of a thin-film transistor of the peripheral driver circuits can be prevented caused by the pressure from the sealing portion.
摘要翻译：通过层叠各种构成薄膜晶体管的薄膜形成的层叠间隔部分设置在外围驱动电路中。结果，即使在密封构件的一部分设置在外围驱动电路的上方的结构中，由密封构件中的间隔物施加的压力集中在层叠间隔部分上，从而破坏周边的薄膜晶体管可以防止来自密封部的压力引起的驱动电路。

94. 发明申请

US20070287202A1 Method for Producing Nano-Scale Low-Dimensional Quantum Structure, and Method for Producing Integrated Circuit Using the Method for Producing the Structure 审中-公开
标题翻译：使用生产结构的方法生产纳米尺度的低维量子结构的方法和生产集成电路的方法
公开(公告)号：US20070287202A1
公开(公告)日：2007-12-13
申请号：US11660931
申请日：2005-08-30
申请人： Kenzo Maehashi , Yasuyuki Fujiwara , Koichi Inoue , Kazuhiko Matsumoto , Yasuhide Ohno
发明人： Kenzo Maehashi , Yasuyuki Fujiwara , Koichi Inoue , Kazuhiko Matsumoto , Yasuhide Ohno
IPC分类号： H01L21/71 , C25B5/00
CPC分类号： B82Y40/00 , B82Y10/00 , B82Y30/00 , C01B32/162 , H01L51/0048
摘要： A method of an embodiment of the present of the present application is for producing a nano-scale low dimensional quantum structure. The method includes: bringing a catalyst on a substrate into contact with vaporized carbon source, and emitting an electromagnetic wave to the catalyst so as to form single-walled carbon nano-tubes on the catalyst. As a result, it is possible to form the nano-scale low-dimensional quantum structure on a target area.
摘要翻译：本申请的本发明的实施方案的方法是用于生产纳米尺度的低维量子结构。该方法包括：使催化剂在基板上与汽化碳源接触，并向催化剂发射电磁波，从而在催化剂上形成单壁碳纳米管。结果，可以在目标区域上形成纳米级的低维量子结构。

95. 发明授权

US07211495B2 Semiconductor devices having a capacitor and methods of manufacturing the same 有权
标题翻译：具有电容器的半导体器件及其制造方法
公开(公告)号：US07211495B2
公开(公告)日：2007-05-01
申请号：US10960216
申请日：2004-10-06
申请人： Jeong Ho Park
发明人： Jeong Ho Park
IPC分类号： H01L21/027 , H01L21/71
CPC分类号： H01L23/53295 , H01L21/76846 , H01L23/5223 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having a capacitor and methods of manufacturing the same are disclosed. A disclosed semiconductor device includes a semiconductor substrate; a lower interconnection line on the substrate; an upper interconnection line electrically connected to a first portion of the lower interconnection line; a first metal layer electrically connected to a second portion of the lower interconnection line; a capacitor insulating layer on the first metal layer; and a second metal layer on the capacitor insulating layer, wherein the first metal layer, the capacitor insulating layer and the second metal layer form a capacitor
摘要翻译：公开了具有电容器的半导体器件及其制造方法。所公开的半导体器件包括半导体衬底; 衬底上的下互连线; 电连接到下互连线的第一部分的上互连线; 电连接到下互连线的第二部分的第一金属层; 第一金属层上的电容器绝缘层; 以及所述电容器绝缘层上的第二金属层，其中所述第一金属层，所述电容器绝缘层和所述第二金属层形成电容器

96. 发明授权

US5529957A Method for blocking contamination and stabilizing chip capacitor during attachment using a tape strip 失效
标题翻译：在使用带条附着时阻止污染和稳定芯片电容器的方法
公开(公告)号：US5529957A
公开(公告)日：1996-06-25
申请号：US417633
申请日：1995-04-06
申请人： Ken Chan
发明人： Ken Chan
IPC分类号： H01L23/64 , H05K1/02 , H05K3/30 , H01L21/71 , H01L21/764
CPC分类号： H01L23/642 , H05K3/303 , H05K3/305 , H01L2924/0002 , H05K1/0231 , H05K2201/10515 , H05K2201/10522 , H05K2201/10636 , H05K2203/0191 , H05K2203/0769 , Y02P70/611 , Y02P70/613 , Y10S148/014
摘要： Chip capacitors are attached to an integrated circuit package. Strips of synthetic tape are placed between pairs of chip capacitor pads on the integrated circuit package. The strips of synthetic tape each have a height extending above height of the pairs of chip capacitor pads. In the preferred embodiment, the strips of synthetic tape are strips of polyimide tape. The height of the strips of synthetic tape is selected so that the chip capacitors will be installed at a sufficient distance from the integrated circuit package so that solder balls will not be of sufficient diameter to wedge between the integrated circuit package and the chip capacitors. The chip capacitors are installed over the pairs of chip capacitor pads. The chip capacitors rest on the strips of synthetic tape. For example, the chip capacitors are permanently attached to the pairs of chip capacitors using a solder process. A reflow solder process is then performed. Afterwards, the strips of synthetic tape are removed from the integrated circuit package. After removal of the strips of synthetic tape, a cleaning of area under the chip capacitors may be performed to remove any material under and around the chip capacitors.
摘要翻译：芯片电容器连接到集成电路封装。合成胶带条放置在集成电路封装上的芯片电容器垫对之间。合成胶带的每条带都具有高于成对的芯片电容器垫的高度的高度。在优选实施例中，合成带的条带是聚酰亚胺胶带条。选择合成胶带条的高度，使得片状电容器将安装在与集成电路封装件足够的距离处，使得焊球不会具有足够的直径以楔住集成电路封装和芯片电容器之间。芯片电容器安装在成对的芯片电容器焊盘上。贴片电容器放在合成胶带上。例如，使用焊接工艺将芯片电容器永久地附接到成对的芯片电容器。然后进行回流焊接工艺。之后，从集成电路封装中取出合成胶带条。在去除合成胶带条之后，可以对芯片电容器下的区域进行清洁以去除芯片电容器下面和周围的任何材料。

97. 发明授权

US11990372B2 Methods of manufacturing semiconductor chip including crack propagation guide 有权
公开(公告)号：US11990372B2
公开(公告)日：2024-05-21
申请号：US17707282
申请日：2022-03-29
申请人： SK hynix Inc.
发明人： In Su Park , Jung Dal Choi
IPC分类号： H01L21/78 , H01L21/71 , H10B43/27
CPC分类号： H01L21/78 , H01L21/71 , H10B43/27
摘要： There may be provided a method of manufacturing a semiconductor chip. A layer stack in which first material layers and second material layers are alternately stacked is formed on a semiconductor substrate that includes a chip region and a scribe lane region, and crack propagation guides are formed in a first portion of the layer stack within the scribe lane region.

98. 发明授权

US11626366B2 Shielding using layers with staggered trenches 有权
公开(公告)号：US11626366B2
公开(公告)日：2023-04-11
申请号：US17360793
申请日：2021-06-28
申请人： Silicon Laboratories Inc.
发明人： Thomas C. Fowler , Jerome T. Wenske
IPC分类号： H01L23/522 , H01L21/71 , H01L23/00 , H01L49/02
摘要： An integrated circuit includes a capacitor with a bottom conductive plate and a top conductive plate. A passivation layer is disposed above the top conductive plate. An intermetal dielectric layer is disposed between the bottom conductive plate and the top conductive plate and is formed of a first dielectric material. Shield layers are disposed between the top conductive plate and above the intermetal dielectric layer and extend horizontally to at least past guard rings. The shield layers include a dielectric layer formed of dielectric material having a dielectric constant greater than the material of the intermetal dielectric layer. The shield layers include horizontally offset trenches to stop horizontal flow of current in the shield layers. The offset ensures there is no vertical path from the passivation layer to lower/ground potentials through the shield layers.

99. 发明授权

US10636731B2 Mechanically flexible interconnects, methods of making the same, and methods of use 有权
公开(公告)号：US10636731B2
公开(公告)日：2020-04-28
申请号：US15744302
申请日：2016-07-14
申请人： Georgia Tech Research Corporation
发明人： Muhannad S. Bakir , Paul Kim Jo
IPC分类号： H01L23/498 , H01L21/48 , H01L21/71 , H01L23/00
CPC分类号： H01L23/49811 , H01L21/4853 , H01L21/71 , H01L24/16 , H01L2924/01029
摘要： Disclosed are various embodiments that involve mechanically flexible interconnects, methods of making mechanically flexible interconnects, methods of using mechanically flexible interconnects, and the like.

100. 再颁专利

USRE47570E1 Stressed substrates for transient electronic systems 有权
公开(公告)号：USRE47570E1
公开(公告)日：2019-08-13
申请号：US15726944
申请日：2017-10-06
申请人： Palo Alto Research Center Incorporated
发明人： Scott J. H. Limb , Gregory L. Whiting , Sean R. Garner , JengPing Lu , Dirk De Bruyker
IPC分类号： H01L21/64 , H01L21/71 , H01L23/14 , H01L27/00 , H03K19/177
CPC分类号： H01L21/71 , H03K19/17768 , H01L21/64 , H01L27/00
摘要： A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event.

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