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91. 发明授权

US5606528A Semiconductor memory device allowing data rewriting electrically 失效
标题翻译：半导体存储器件允许电气数据重写
公开(公告)号：US5606528A
公开(公告)日：1997-02-25
申请号：US553910
申请日：1995-11-06
申请人： Yutaka Ikeda
发明人： Yutaka Ikeda
IPC分类号： G11C11/401 , G11C11/409 , G11C29/00 , G11C29/04 , G11C29/06 , G11C29/34 , G11C8/00
CPC分类号： G11C29/34
摘要： A memory array block MK of the same structure is arranged in all the memory array regions MA of a DRAM. An IO line control circuit connects the other end of a pair of local signal input/output lines to one end of a pair of global signal input/output lines in an opposite phase or a positive phase in response to one end of the corresponding pair of local signal input/output lines being connected to an even numbered bit line pair of the upper row of memory array region MA or an odd numbered bit line pair of the lower row of memory array region MA. Since the memory array blocks MK in all the memory array region MA have the same structure, a memory cell corresponding to a defective address detected in a BI test can easily be identified.
摘要翻译：具有相同结构的存储器阵列块MK被布置在DRAM的所有存储器阵列区域MA中。 IO线路控制电路将一对本地信号输入/输出线路的另一端连接到一对全局信号输入/输出线路的一端，以响应相应的一对本地信号输入/输出线连接到存储器阵列区域MA的上一行或存储器阵列区域MA的下行的奇数位线对中的偶数位线对。由于所有存储器阵列区域MA中的存储器阵列块MK具有相同的结构，因此可以容易地识别与在BI测试中检测到的缺陷地址相对应的存储单元。

92. 发明授权

US5568436A Semiconductor device and method of screening the same 失效
公开(公告)号：US5568436A
公开(公告)日：1996-10-22
申请号：US480926
申请日：1995-06-07
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C11/408 , G11C11/409 , G11C29/00 , G11C29/06 , G11C29/46 , G11C29/50 , G11C7/00 , G11C8/00
CPC分类号： G11C11/4085 , G11C29/46 , G11C29/50 , G11C5/145 , G11C5/147 , G11C11/401
摘要： A semiconductor device comprising a plurality of circuit blocks to which various potentials, including at least one potential either raised or lowered, are assigned. The device further comprises means for selectively and reversely changing the potentials assigned to the circuit blocks.

93. 发明授权

US5544123A Semiconductor memory device having a test circuit 失效
标题翻译：具有测试电路的半导体存储器件
公开(公告)号：US5544123A
公开(公告)日：1996-08-06
申请号：US395031
申请日：1995-02-27
申请人： Satoru Hoshi , Masami Masuda
发明人： Satoru Hoshi , Masami Masuda
IPC分类号： G01R31/28 , G11C8/10 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , G11C29/34 , G11C29/50 , G11C8/00
CPC分类号： G11C29/34 , G11C29/50 , G11C8/10 , G11C11/401
摘要： A plurality of voltage supply circuits each including an inverter circuit are provided at the final stage of a row decoder. The voltage supply circuits are supplied with voltage Vdd and voltage Vxx. The voltage Vxx is set at a level of Vss in a normal operation mode and at a level higher than that of Vdd in a burn-in test mode. In the latter mode, the voltage Vdd is applied to the voltage supply circuit connected to a selected word line, while the voltage Vxx (higher than Vdd) is applied to the voltage supply circuit connected to a nonselected word line. All word lines are therefore set at a high level and rendered in a selective state.
摘要翻译：在行解码器的最后一级设置有包括反相器电路的多个电压供给电路。电压供给电路被供给电压Vdd和电压Vxx。电压Vxx在正常工作模式下设定在Vss的电平，并且在老化测试模式下设定为高于Vdd的电平。在后一种模式中，电压Vdd被施加到连接到所选字线的电压供应电路，而电压Vxx（高于Vdd）被施加到连接到非选择字线的电压供应电路。因此，所有字线被设置在高电平并且呈现在选择状态。

94. 发明授权

US5519652A Nonvolatile semiconductor memory for positively holding stored data 失效
标题翻译：用于积极保存存储数据的非易失性半导体存储器
公开(公告)号：US5519652A
公开(公告)日：1996-05-21
申请号：US158796
申请日：1993-12-01
申请人： Sinsuke Kumakura , Yasushige Ogawa , Takao Akaogi , Tetsuya Chida
发明人： Sinsuke Kumakura , Yasushige Ogawa , Takao Akaogi , Tetsuya Chida
IPC分类号： G11C17/00 , G11C16/06 , G11C16/26 , G11C16/28 , G11C29/00 , G11C29/06 , G11C29/50 , G11C29/56 , G11C11/34
CPC分类号： G11C29/50016 , G11C16/26 , G11C16/28 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/5006
摘要： A semiconductor memory has a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a differential sense amplifier, and load transistors. Each of the memory cells is a MIS transistor formed at each intersection of the word and bit lines. The threshold voltage of the MIS transistor is externally electrically controllable. The differential sense amplifier senses data stored in a selected memory cell located at an intersection of selected word and bit lines. A control pulse signal is applied to the gates of the load transistors, to bias the bit lines. The pulse width of the control pulse signal is a minimum essential to read data out of the selected memory cell. The control pulse signal controls the switching of the load transistors, to shorten a period during which a stress voltage is continuously applied to the drains of unselected memory cells that are connected to the bit line to which the selected memory cell is connected.
摘要翻译：半导体存储器具有多个字线，多个位线，多个存储单元，差分读出放大器和负载晶体管。每个存储单元是形成在字和位线的每个交叉处的MIS晶体管。 MIS晶体管的阈值电压是外部电可控的。差分读出放大器感测存储在位于选定字和位线的交叉点处的选定存储单元中的数据。控制脉冲信号施加到负载晶体管的栅极，以偏置位线。控制脉冲信号的脉冲宽度是从所选存储单元读出数据所必需的最小值。控制脉冲信号控制负载晶体管的切换，以缩短连续施加到与所选存储单元连接的位线的未选择存储单元的漏极的应力电压的周期。

95. 发明授权

US5424988A Stress test for memory arrays in integrated circuits 失效
标题翻译：集成电路中存储器阵列的压力测试
公开(公告)号：US5424988A
公开(公告)日：1995-06-13
申请号：US954276
申请日：1992-09-30
申请人： David C. McClure , James Brady
发明人： David C. McClure , James Brady
IPC分类号： G01R31/28 , G11C11/413 , G11C29/00 , G11C29/06 , G11C29/34 , G11C29/50 , G11C7/00
CPC分类号： G11C29/34 , G11C29/50 , G11C11/41
摘要： A method for stress testing a memory array in an integrated circuit. Control circuitry selects a plurality of row lines at one time. An overvoltage suitable for stressing the cells of the array is placed on the bit lines. Because a block of cells has been selected, the overvoltage is applied to all cells of the block. The block of cells selected may be either the entire memory array or a portion of the memory array. The selected rows remain selected for the duration of the stress test. Because the overvoltage is applied directly to selected cells, the full overvoltage will be used to stress the transistor gates for the entire test period. In this manner, latent defects within the memory array can be detected.
摘要翻译：一种用于对集成电路中的存储器阵列进行应力测试的方法。控制电路一次选择多行行。适用于对阵列的单元进行加压的过电压放置在位线上。因为已经选择了一个单元块，所以过电压被施加到该块的所有单元。所选择的单元块可以是整个存储器阵列或存储器阵列的一部分。所选行在压力测试期间保持选择。因为过电压直接应用于所选择的单元，所以在整个测试周期中，将使用全过电压来施加晶体管栅极。以这种方式，可以检测存储器阵列内的潜在缺陷。

96. 发明授权

US5365482A Semiconductor memory device with provision of pseudo-acceleration test 失效
标题翻译：半导体存储器件提供伪加速度测试
公开(公告)号：US5365482A
公开(公告)日：1994-11-15
申请号：US181467
申请日：1994-01-13
申请人： Hiroshi Nakayama
发明人： Hiroshi Nakayama
IPC分类号： G11C11/413 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/02 , G11C29/06 , G11C29/50
CPC分类号： G11C29/021 , G11C29/02 , G11C29/50 , G11C29/50012 , G11C11/401 , G11C11/41
摘要： In a semiconductor memory device including memory cells connected to word lines, one of the word lines is selected by a word line selecting circuit. A word line driving circuit receives an activation signal and a pseudo-acceleration signal to generate a driving signal for driving the selecting circuit. The driving signal is generated by delaying the activation signal with a definite delay time period which is changed in response to the pseudo-acceleration test signal, to thus perform a pseudo-acceleration test upon the word line driving circuit.
摘要翻译：在包括连接到字线的存储单元的半导体存储器件中，字线选择电路中选择一个字线。字线驱动电路接收激活信号和伪加速度信号以产生用于驱动选择电路的驱动信号。驱动信号是通过延迟具有响应于伪加速度测试信号而改变的确定延迟时间周期的激活信号而产生的，从而对字线驱动电路进行伪加速度测试。

97. 发明授权

US5355342A Semiconductor memory device having multiple selector unit simultaneously selecting memory cells from memory cell blocks in diagnostic mode of operation 失效
标题翻译：具有多个选择器单元的半导体存储器件在诊断操作模式下从存储器单元块中同时选择存储器单元
公开(公告)号：US5355342A
公开(公告)日：1994-10-11
申请号：US52665
申请日：1993-04-27
申请人： Junji Ueoka
发明人： Junji Ueoka
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/28 , G11C29/34 , G11C29/50 , G11C7/00
CPC分类号： G11C29/28 , G11C29/50
摘要： A semiconductor memory device is subjected to a dynamic bias test upon completion of a fabrication process for screening out a product with potential defects, and a block selecting unit incorporated in the semiconductor memory device is responsive to block address bits for allowing an external device to access data bits stored in one of the memory cell blocks, wherein the block selecting unit is further responsive to a test signal indicative of the dynamic bias test for allowing a diagnostic system to write test bits into or read out the test bits from all of the memory cell blocks, thereby quickly completing the dynamic bias test.
摘要翻译：半导体存储器件在完成用于筛选具有潜在缺陷的产品的制造过程中经受动态偏置测试，并且结合在半导体存储器件中的块选择单元响应于块地址位以允许外部器件访问存储在存储单元块之一中的数据位，其中块选择单元进一步响应指示动态偏置测试的测试信号，以允许诊断系统将测试位写入或从所有存储器中读出测试位从而快速完成动态偏置测试。

98. 发明授权

US5337272A Circuit for applying selected voltages to dynamic random access memory 失效
标题翻译：将选定电压应用于动态随机存取存储器有效老化和存储单元测试的电路
公开(公告)号：US5337272A
公开(公告)日：1994-08-09
申请号：US32554
申请日：1993-03-17
申请人： Makoto Suwa , Hiroshi Miyamoto , Shigeru Mori
发明人： Makoto Suwa , Hiroshi Miyamoto , Shigeru Mori
IPC分类号： G11C11/404 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/50 , G11C11/40 , G11C11/407
CPC分类号： G11C29/50008 , G11C29/50 , G11C11/401
摘要： A dynamic random access memory (DRAM) includes a selection circuit for selecting the voltages used for aging. The selection circuit operates responsive to external control signals. When a source voltage (Vcc) is selected, the voltage (Vcc) is supplied to one electrode of a memory cell via a circuit 73 and a transmission gate while a ground potential (Vss) is supplied to the other electrode via a bit line and a transistor. Conversely, when the ground potential (Vss) is selected, an inverted voltage is applied across the two electrodes. In this manner, the insulating properties of an insulator interposed between the two electrodes can be checked more reliably during aging.
摘要翻译：动态随机存取存储器（DRAM）包括用于选择用于老化的电压的选择电路。选择电路响应于外部控制信号而工作。当选择源电压（Vcc）时，经由电路73和传输栅极将电压（Vcc）提供给存储单元的一个电极，同时通过位线将地电位（Vss）提供给另一电极，一个晶体管。相反，当选择接地电位（Vss）时，在两个电极之间施加反向电压。以这种方式，可以在老化期间更可靠地检查插入在两个电极之间的绝缘体的绝缘性。

99. 发明授权

US5303193A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5303193A
公开(公告)日：1994-04-12
申请号：US813580
申请日：1991-12-26
申请人： Masaki Ogihara
发明人： Masaki Ogihara
IPC分类号： G01R31/28 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/50 , H01L21/66 , H01L21/822 , H01L27/04 , G11C7/00
CPC分类号： G11C29/50 , G11C11/401
摘要： According to this invention, a semiconductor device includes a plurality of MOS transistors arranged in a matrix form, common wiring lines connected to MOS transistors of the same row or the same column, diodes each having one end connected to a corresponding one of the common wiring lines of each row or column, and a voltage applying circuit for controlling the potential of other terminal of each of the diodes and simultaneously applying a predetermined voltage to all the common wiring lines or arbitrary common wiring lines having the number larger than the number of wiring lines selected during a normal operation.
摘要翻译：根据本发明，半导体器件包括以矩阵形式布置的多个MOS晶体管，连接到同一列或同一列的MOS晶体管的公共布线，每个具有一端连接到相应的一条公共布线每行或列的行，以及用于控制每个二极管的其他端子的电位的电压施加电路，并且同时向所有公共布线或具有大于布线数量的任意公共布线施加预定电压在正常操作期间选择的线。

100. 发明授权

US5282167A Dynamic random access memory 失效
标题翻译：动态随机存取存储器
公开(公告)号：US5282167A
公开(公告)日：1994-01-25
申请号：US813674
申请日：1991-12-26
申请人： Hiroaki Tanaka , Masaru Koyanagi
发明人： Hiroaki Tanaka , Masaru Koyanagi
IPC分类号： G01R31/28 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/06 , G11C29/50 , H01L21/66 , G11C7/02
CPC分类号： G11C29/50 , G11C11/4085 , G11C11/401
摘要： A DRAM according to the invention has noise-eliminating circuits. Each of the circuits has an output side thereof connected to a corresponding word line. At the time of a voltage stress examination, each of the circuits is controlled to be in an on-state thereby transmitting a voltage stress, input an input side thereof, to the word line. At the time of normal operation, the input side of the circuit is connected to an earth node, and each of the circuits is turned on and off in accordance with a signal output from a corresponding one of word line-selecting circuits or with the level of a corresponding one of the word lines.
摘要翻译：根据本发明的DRAM具有消噪电路。每个电路的输出侧连接到相应的字线。在电压胁迫检查时，每个电路被控制为导通状态，从而将电压应力传输到字线。在正常操作时，电路的输入端连接到接地节点，并且每个电路根据从相应的一个字线选择电路输出的信号或者与电平对应的一行字线。

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