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1. 发明授权

US5566386A Nonvolatile semiconductor memory device having a status register and test method for the same 失效
标题翻译：具有状态寄存器的非易失性半导体存储器件及其测试方法
公开(公告)号：US5566386A
公开(公告)日：1996-10-15
申请号：US471526
申请日：1995-06-06
申请人： Sinsuke Kumakura , Hirokazu Yamazaki , Hisayoshi Watanabe , Yasushi Kasa
发明人： Sinsuke Kumakura , Hirokazu Yamazaki , Hisayoshi Watanabe , Yasushi Kasa
IPC分类号： G01R31/28 , G11C5/14 , G11C7/06 , G11C16/06 , G11C17/00 , G11C29/00 , G11C29/02 , G11C29/24 , G11C29/44 , G11C29/50 , H01L21/8247 , H01L27/115
CPC分类号： G11C29/021 , G11C29/02 , G11C29/24 , G11C29/44 , G11C29/50 , G11C29/50004 , G11C29/50016 , G11C5/14 , G11C5/143 , G11C7/062 , G11C16/04 , G11C2029/5006
摘要： An object of the present invention is to provided a semiconductor device that permits easy and efficient testing. A semiconductor device which is characterized in that the power supply for an output circuit is selectable between a normal power supply and an independent power supply provided independently of the normal supply.
摘要翻译：本发明的目的是提供一种允许容易和有效测试的半导体器件。一种半导体器件，其特征在于，用于输出电路的电源可在普通电源和独立于正常供电设置的独立电源之间进行选择。

2. 发明授权

US5592427A Semiconductor memory having a sense amplifier with load transistors having different load characteristics 失效
标题翻译：半导体存储器具有具有不同负载特性的负载晶体管的读出放大器
公开(公告)号：US5592427A
公开(公告)日：1997-01-07
申请号：US463636
申请日：1995-06-06
申请人： Sinsuke Kumakura , Hirokazu Yamazaki , Hisayoshi Watanabe , Yasushi Kasa
发明人： Sinsuke Kumakura , Hirokazu Yamazaki , Hisayoshi Watanabe , Yasushi Kasa
IPC分类号： G01R31/28 , G11C5/14 , G11C7/06 , G11C16/06 , G11C17/00 , G11C29/00 , G11C29/02 , G11C29/24 , G11C29/44 , G11C29/50 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C29/021 , G11C29/02 , G11C29/24 , G11C29/44 , G11C29/50 , G11C29/50004 , G11C29/50016 , G11C5/14 , G11C5/143 , G11C7/062 , G11C16/04 , G11C2029/5006
摘要： An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3, . . . , whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.
摘要翻译：本发明的目的是提供一种能够容易且有效地进行测试的半导体器件。非易失性半导体存储器包括字线WLi和位线BLi，由非易失性存储单元Cij组成的存储单元矩阵17，读出放大器15，用于执行写和擦除操作所需的定时控制的写/擦除定时电路9，以及状态寄存器2，用于在电路9的操作完成时存储存储器的操作状态，其中在存储单元矩阵17的地址之外提供两种虚拟单元D1，D2，D3。。。，其值固定为从感测放大器15引起不同输出的不同值。通过访问虚拟单元来产生通过条件或失败条件。

3. 发明授权

US5469394A Nonvolatile semiconductor memory device having a status register and test method for the same 失效
标题翻译：具有状态寄存器的非易失性半导体存储器件及其测试方法
公开(公告)号：US5469394A
公开(公告)日：1995-11-21
申请号：US365847
申请日：1994-12-29
申请人： Sinsuke Kumakura , Hirokazu Yamazaki , Hisayoshi Watanabe , Yasushi Kasa
发明人： Sinsuke Kumakura , Hirokazu Yamazaki , Hisayoshi Watanabe , Yasushi Kasa
IPC分类号： G01R31/28 , G11C5/14 , G11C7/06 , G11C16/06 , G11C17/00 , G11C29/00 , G11C29/02 , G11C29/24 , G11C29/44 , G11C29/50 , H01L21/8247 , H01L27/115 , G11C7/00 , G01R31/26 , H01L21/66
CPC分类号： G11C29/021 , G11C29/02 , G11C29/24 , G11C29/44 , G11C29/50 , G11C29/50004 , G11C29/50016 , G11C5/14 , G11C5/143 , G11C7/062 , G11C16/04 , G11C2029/5006
摘要： An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3, . . . , whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.
摘要翻译：本发明的目的是提供一种能够容易且有效地进行测试的半导体器件。非易失性半导体存储器包括字线WLi和位线BLi，由非易失性存储单元Cij组成的存储单元矩阵17，读出放大器15，用于执行写和擦除操作所需的定时控制的写/擦除定时电路9，以及状态寄存器2，用于在电路9的操作完成时存储存储器的操作状态，其中在存储单元矩阵17的地址之外提供两种虚拟单元D1，D2，D3。。。，其值固定为从感测放大器15引起不同输出的不同值。通过访问虚拟单元来产生通过条件或失败条件。

4. 发明授权

US5291046A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5291046A
公开(公告)日：1994-03-01
申请号：US831963
申请日：1992-02-06
申请人： Sinsuke Kumakura
发明人： Sinsuke Kumakura
IPC分类号： G11C17/00 , G11C16/04 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L29/68
CPC分类号： G11C16/0416
摘要： A control gate formed on top of an insulation layer over a floating gate for a transistor element of a memory cell in a redundancy ROM is shaped in a form covering not only the top but also the sides of the floating gate. A drain electrode wiring conventionally connected through a well is directly connected to a drain diffusion area. This enables the redundancy ROM to be miniaturized and the voltage fall at the edge of a drain diffusion area to be reduced.
摘要翻译：形成在冗余ROM中的存储单元的晶体管元件的浮栅上的绝缘层顶部的控制栅被成形为不仅覆盖浮动栅极的顶部而且覆盖侧面的形式。通常通过阱连接的漏电极布线直接连接到漏极扩散区域。这使得能够使冗余ROM小型化并且降低漏极扩散区域的边缘处的电压。

5. 发明授权

US5412337A Semiconductor device providing reliable conduction test of all terminals 失效
标题翻译：半导体器件提供所有端子的可靠导通测试
公开(公告)号：US5412337A
公开(公告)日：1995-05-02
申请号：US297717
申请日：1994-08-30
申请人： Sinsuke Kumakura
发明人： Sinsuke Kumakura
IPC分类号： G01R31/26 , G01R31/02 , G01R31/04 , G01R31/28 , G01R31/30 , G11C29/00 , G11C29/56 , H01L25/00
CPC分类号： G01R31/04 , G01R31/3004 , H01L2924/0002
摘要： A semiconductor device is disclosed which is directed to drastically reduce a conduction test time by reliably executing the conduction test of all terminals in a lump. The invention discloses the semiconductor device including a first power supply terminal, a second power supply terminal having a lower potential than the first power supply terminal, an internal circuit portion to which the first and second power supply terminals are connected, and an input signal terminal group and an output signal terminal group each connected to the internal circuit portion, wherein a first voltage supply source and a second voltage supply source having a predetermined potential difference from the first voltage supply source are disposed, a switching device is interposed between the first and second voltage supply sources, and the switching device is turned ON and OFF in accordance with the existence of a voltage applied to each of the terminals described above.
摘要翻译：公开了一种半导体器件，其旨在通过可靠地执行所有端子的导通测试来大幅度地减少导通测试时间。本发明公开了一种半导体器件，包括第一电源端子，具有比第一电源端子低的电位的第二电源端子，连接第一和第二电源端子的内部电路部分，以及输入信号端子组和输出信号端子组，每个连接到内部电路部分，其中设置有与第一电压源具有预定电位差的第一电压源和第二电压源，切换装置插入在第一和第二电压源，并且根据施加到上述每个端子的电压的存在而将开关装置导通和截止。

6. 发明授权

US5402380A Nonvolatile semiconductor memory device having a status register and test method for the same 失效
标题翻译：具有状态寄存器的非易失性半导体存储器件及其测试方法
公开(公告)号：US5402380A
公开(公告)日：1995-03-28
申请号：US192821
申请日：1994-02-07
申请人： Sinsuke Kumakura , Hirokazu Yamazaki , Hisayoshi Watanabe , Yasushi Kasa
发明人： Sinsuke Kumakura , Hirokazu Yamazaki , Hisayoshi Watanabe , Yasushi Kasa
IPC分类号： G01R31/28 , G11C5/14 , G11C7/06 , G11C16/06 , G11C17/00 , G11C29/00 , G11C29/02 , G11C29/24 , G11C29/44 , G11C29/50 , H01L21/8247 , H01L27/115 , G11C7/02
CPC分类号： G11C29/021 , G11C29/02 , G11C29/24 , G11C29/44 , G11C29/50 , G11C29/50004 , G11C29/50016 , G11C5/14 , G11C5/143 , G11C7/062 , G11C16/04 , G11C2029/5006
摘要： An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory including word lines WLi and bit lines BLi, a memory cell matrix 17 including nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3, . . . , whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.
摘要翻译：本发明的目的是提供一种能够容易且有效地进行测试的半导体器件。包括字线WLi和位线BLi的非易失性半导体存储器，包括非易失性存储单元Cij的存储单元矩阵17，读出放大器15，用于执行写入和擦除操作所需的定时控制的写入/擦除定时电路9以及状态寄存器2，用于在电路9的操作完成时存储存储器的工作状态，其中在存储单元矩阵17的地址之外提供两种虚拟单元D1，D2，D3。。。，其值固定为从感测放大器15引起不同输出的不同值。通过访问虚拟单元来产生通过条件或失败条件。

7. 发明授权

US5519652A Nonvolatile semiconductor memory for positively holding stored data 失效
标题翻译：用于积极保存存储数据的非易失性半导体存储器
公开(公告)号：US5519652A
公开(公告)日：1996-05-21
申请号：US158796
申请日：1993-12-01
申请人： Sinsuke Kumakura , Yasushige Ogawa , Takao Akaogi , Tetsuya Chida
发明人： Sinsuke Kumakura , Yasushige Ogawa , Takao Akaogi , Tetsuya Chida
IPC分类号： G11C17/00 , G11C16/06 , G11C16/26 , G11C16/28 , G11C29/00 , G11C29/06 , G11C29/50 , G11C29/56 , G11C11/34
CPC分类号： G11C29/50016 , G11C16/26 , G11C16/28 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/5006
摘要： A semiconductor memory has a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a differential sense amplifier, and load transistors. Each of the memory cells is a MIS transistor formed at each intersection of the word and bit lines. The threshold voltage of the MIS transistor is externally electrically controllable. The differential sense amplifier senses data stored in a selected memory cell located at an intersection of selected word and bit lines. A control pulse signal is applied to the gates of the load transistors, to bias the bit lines. The pulse width of the control pulse signal is a minimum essential to read data out of the selected memory cell. The control pulse signal controls the switching of the load transistors, to shorten a period during which a stress voltage is continuously applied to the drains of unselected memory cells that are connected to the bit line to which the selected memory cell is connected.
摘要翻译：半导体存储器具有多个字线，多个位线，多个存储单元，差分读出放大器和负载晶体管。每个存储单元是形成在字和位线的每个交叉处的MIS晶体管。 MIS晶体管的阈值电压是外部电可控的。差分读出放大器感测存储在位于选定字和位线的交叉点处的选定存储单元中的数据。控制脉冲信号施加到负载晶体管的栅极，以偏置位线。控制脉冲信号的脉冲宽度是从所选存储单元读出数据所必需的最小值。控制脉冲信号控制负载晶体管的切换，以缩短连续施加到与所选存储单元连接的位线的未选择存储单元的漏极的应力电压的周期。

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