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91. 发明授权

US06936502B2 Package modification for channel-routed circuit boards 失效
标题翻译：通道路由电路板的封装修改
公开(公告)号：US06936502B2
公开(公告)日：2005-08-30
申请号：US10437006
申请日：2003-05-14
申请人： Aneta Wyrzykowska , Herman Kwong , Luigi Difilippo
发明人： Aneta Wyrzykowska , Herman Kwong , Luigi Difilippo
IPC分类号： H05K1/11 , H05K3/30 , H05K3/46 , H01L21/60 , H05K3/32
CPC分类号： H05K1/112 , H01L2224/14 , H01L2224/17 , H01L2924/00014 , H05K3/303 , H05K3/4623 , H05K2201/09472 , H05K2201/09518 , H05K2201/09536 , H05K2201/10318 , H05K2201/10424 , H05K2201/10659 , H05K2201/10704 , H05K2201/10734 , Y02P70/613 , Y10T29/4913 , Y10T29/49135 , Y10T29/49139 , Y10T29/49147 , Y10T29/49165 , H01L2224/0401
摘要： A method for implementing a circuit component on a surface of a multilayer circuit board is provided. The circuit component includes a plurality of pins and the circuit board includes a plurality of electrically conductive vias penetrating at least one layer of the circuit board and being arranged so as to form at least one channel for routing one or more traces at one or more signal layers of the circuit board. The method comprises the step of forming at least one pin of the plurality of pins of the circuit component to have a length compatible with a depth of a corresponding via of the circuit board.
摘要翻译：提供一种在多层电路板的表面上实现电路元件的方法。电路部件包括多个引脚，并且电路板包括穿透电路板的至少一个层的多个导电通孔，并被布置成形成用于在一个或多个信号处路由一个或多个迹线的至少一个通道层的电路板。该方法包括以下步骤：形成电路部件的多个引脚中的至少一个引脚以具有与电路板的相应通孔的深度相兼容的长度。

92. 发明授权

US06917509B1 Single layer capacitor with dissimilar metallizations 有权
标题翻译：具有不同金属化的单层电容器
公开(公告)号：US06917509B1
公开(公告)日：2005-07-12
申请号：US10301335
申请日：2002-11-21
申请人： Daniel F. Devoe , Lambert Devoe , Alan D. Devoe
发明人： Daniel F. Devoe , Lambert Devoe , Alan D. Devoe
IPC分类号： H01G2/06 , H01G4/228 , H05K3/32 , H05K3/34 , H01G4/008 , H01G4/06
CPC分类号： H01G4/228 , H01G2/065 , H01L2224/48091 , H01L2924/19107 , H05K3/328 , H05K3/341 , H05K2201/10643 , H05K2201/10659 , H05K2201/10909 , H05K2203/049 , H01L2924/00014
摘要： A single layer ceramic capacitor for wire bonding or solder or epoxy attachment wherein a bottom metallization is of a lesser purity than a top metallization whereby the bottom metallization may be effectively soldered without leaching of the metal and the top metallization may be wire bonded. In an exemplary embodiment, the top metallization is essentially pure gold and the bottom metallization is an alloy of gold and platinum and/or palladium. The top and bottom metallizations are provided on a dielectric body that advantageously comprises a ceramic having a sintering temperature below the melting point of gold. In a further exemplary embodiment, the capacitance of the capacitor may be enhanced by providing one or more interior metallization planes parallel to the exterior metallizations and connected thereto by conductive vias.
摘要翻译：用于引线接合或焊料或环氧树脂附着的单层陶瓷电容器，其中底部金属化的纯度比顶部金属化的纯度低，由此底部金属化可以有效地焊接而不会浸出金属，并且顶部金属化可以是引线键合的。在示例性实施例中，顶部金属化基本上是纯金，底部金属化是金和铂和/或钯的合金。顶部和底部金属化物提供在电介质体上，其有利地包括具有低于金熔点的烧结温度的陶瓷。在另一示例性实施例中，可以通过提供一个或多个内部金属化平面平行于外部金属化并通过导电通孔与其连接的电容来增强电容器的电容。

93. 发明授权

US06911733B2 Semiconductor device and electronic device 失效
标题翻译：半导体器件和电子器件
公开(公告)号：US06911733B2
公开(公告)日：2005-06-28
申请号：US10372898
申请日：2003-02-26
申请人： Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
发明人： Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
IPC分类号： H01L23/66 , H05K1/02 , H05K3/36 , H01L23/34
CPC分类号： H05K1/0243 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2224/16 , H01L2224/16225 , H01L2224/32188 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/01079 , H01L2924/09701 , H01L2924/15173 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/16152 , H01L2924/1903 , H01L2924/19106 , H01L2924/3011 , H01L2924/3025 , H05K1/0219 , H05K3/361 , H05K2201/10522 , H05K2201/1053 , H05K2201/10659 , H05K2201/10681 , H05K2201/10734 , H01L2924/00014 , H01L2924/00
摘要： A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.
摘要翻译：来自具有布置在其两侧的表面层信号引线和表面层GND引线的带状线段的高频信号经由封装衬底的信号表面层布线直接输入到半导体芯片，并通过焊料凸块电极。或者，来自半导体芯片的高频信号经由带状线路部分反向输出到外部。由于仅在封装衬底的整个表面层处的微带线传输高频信号，所以高频信号可以仅通过表层的微带线传输，而不需要通过通孔等。因此，可以不损失频率特性来发送高频信号，并且可以在高频率传输时以低损耗的方式发送高质量的高频信号。

94. 发明申请

US20050077610A1 Ball grid array package with external leads 审中-公开
标题翻译：具有外部引线的球栅阵列封装
公开(公告)号：US20050077610A1
公开(公告)日：2005-04-14
申请号：US10680099
申请日：2003-10-08
申请人： Tzyy Tan , Suet Woon , Say Tan
发明人： Tzyy Tan , Suet Woon , Say Tan
IPC分类号： H01L23/31 , H01L23/495 , H01L23/498 , H05K3/34 , H01L23/48
CPC分类号： H01L23/495 , H01L23/3128 , H01L23/49816 , H01L2924/0002 , H01L2924/1433 , H05K3/341 , H05K3/3415 , H05K3/3421 , H05K3/3436 , H05K3/3447 , H05K2201/10659 , H05K2201/10734 , Y02P70/613 , H01L2924/00
摘要： In some embodiments, a package suitable to contain one or more semiconductor dies includes one or more solder-balls at an underside of said package and one or more external leads at a side edge of said package. Any or all of the solder-balls and external leads may serve as external electrical terminations of the package. The external leads may be surface mount leads and/or through-hole leads. In some embodiments, a printed circuit board may include pads designed to be soldered to solder-balls of a package and pads designed to be soldered to external leads of the package.
摘要翻译：在一些实施例中，适于容纳一个或多个半导体管芯的封装在所述封装的下侧包括一个或多个焊球，以及在所述封装的侧边缘处的一个或多个外部引线。任何或全部焊球和外部引线可用作封装的外部电气终端。外部引线可以是表面贴装引线和/或通孔引线。在一些实施例中，印刷电路板可以包括设计成焊接到封装的焊球的焊盘和设计成焊接到封装的外部引线的焊盘。

95. 发明申请

US20040226742A1 Package modification for channel-routed circuit boards 失效
标题翻译：通道路由电路板的封装修改
公开(公告)号：US20040226742A1
公开(公告)日：2004-11-18
申请号：US10437006
申请日：2003-05-14
发明人： Aneta Wyrzykowska , Herman Kwong , Luigi Difilippo
IPC分类号： H05K007/10
CPC分类号： H05K1/112 , H01L2224/14 , H01L2224/17 , H01L2924/00014 , H05K3/303 , H05K3/4623 , H05K2201/09472 , H05K2201/09518 , H05K2201/09536 , H05K2201/10318 , H05K2201/10424 , H05K2201/10659 , H05K2201/10704 , H05K2201/10734 , Y02P70/613 , Y10T29/4913 , Y10T29/49135 , Y10T29/49139 , Y10T29/49147 , Y10T29/49165 , H01L2224/0401
摘要： A method for implementing a circuit component on a surface of a multilayer circuit board is provided. The circuit component includes a plurality of pins and the circuit board includes a plurality of electrically conductive vias penetrating at least one layer of the circuit board and being arranged so as to form at least one channel for routing one or more traces at one or more signal layers of the circuit board. The method comprises the step of forming at least one pin of the plurality of pins of the circuit component to have a length compatible with a depth of a corresponding via of the circuit board.
摘要翻译：提供一种在多层电路板的表面上实现电路元件的方法。电路部件包括多个引脚，并且电路板包括穿透电路板的至少一个层的多个导电通孔，并被布置成形成用于在一个或多个信号处路由一个或多个迹线的至少一个通道层的电路板。该方法包括以下步骤：形成电路部件的多个引脚中的至少一个引脚以具有与电路板的相应通孔的深度相兼容的长度。

96. 发明申请

US20040062015A1 Surface mounted electrical components 有权
公开(公告)号：US20040062015A1
公开(公告)日：2004-04-01
申请号：US10255312
申请日：2002-09-26
发明人： Yakov Belopolsky
IPC分类号： H05K007/02 , H05K007/06 , H05K007/08 , H05K007/10
CPC分类号： H05K3/3415 , H01L2224/16225 , H01L2924/00014 , H05K3/244 , H05K3/303 , H05K3/3436 , H05K3/3447 , H05K3/3463 , H05K2201/09781 , H05K2201/10659 , H05K2201/10734 , H05K2203/047 , H05K2203/167 , Y02P70/613 , Y10T29/49004 , Y10T29/49121 , Y10T29/4913 , Y10T29/49131 , Y10T29/49144 , Y10T29/49149 , Y10T29/49165 , Y10T29/49222 , H01L2224/0401
摘要： Methods for mounting electrical components on a substrate and securely retaining the components are described. The methods include altering solder paste compositions, interposed between component retentive pins and retentive through holes, during a reflow process. Electronic assemblies including circuit boards and electrical components mounted thereto are also described. In one of the electronic assembly embodiments, materials originally associated with a mounted electrical component migrate into solder paste coupling the electrical component to the circuit board.

97. 发明申请

US20030137808A1 Electronic module having canopy-type carriers 审中-公开
公开(公告)号：US20030137808A1
公开(公告)日：2003-07-24
申请号：US10341522
申请日：2003-01-13
发明人： Kenneth J. Kledzik , Jason C. Engle
IPC分类号： H05K007/20
CPC分类号： H05K1/141 , H01L25/105 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2225/1094 , H01L2924/0002 , H05K1/0231 , H05K3/0061 , H05K3/3405 , H05K3/3421 , H05K3/368 , H05K2201/049 , H05K2201/1034 , H05K2201/10515 , H05K2201/10659 , H05K2201/10689 , H05K2201/10734 , H05K2201/10924 , H01L2924/00
摘要： An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. A second primary embodiment of the invention utilizes a carrier substrate, which has a pair of recesses for back-to-back surface mounting of the IC package pair. The two IC packages may be in contact with opposite sides of a heat sink layer embedded within the carrier substrate. Each resulting IC package unit is surface mounted to the main circuit board. A third primary embodiment of the invention incorporates features of both the first and second primary embodiments. One of the packages is mounted on a planar surface of the carrier right side up, while the other package is mounted on the carrier in a recess upside down. Several variants of this embodiment are possible. Either the IC package that is mounted on the planar surface of the carrier, or the IC package that is mounted within the recess, may be mounted adjacent to the main circuit board. In the former case, the adjacent package of the package unit fits within a recess on the main circuit board. In the latter case, the adjacent package of the package unit mounts on a planar surface of the main circuit board. For any of the three primary main embodiments, the carrier may be equipped with its own set of interconnection leads which interface with the interconnection pads on the main circuit board or connection may be made directly between the leads of one package and the interconnection pads of the circuit board.

98. 发明授权

US06586684B2 Circuit housing clamp and method of manufacture therefor 失效
标题翻译：印刷电路板外壳夹
公开(公告)号：US06586684B2
公开(公告)日：2003-07-01
申请号：US09896409
申请日：2001-06-29
申请人： Kristopher Frutschy , Glenn E. Stewart , Farzaneh Yahyaei-Moayyed , Geoffery L. Reid
发明人： Kristopher Frutschy , Glenn E. Stewart , Farzaneh Yahyaei-Moayyed , Geoffery L. Reid
IPC分类号： H05K116
CPC分类号： H05K1/0263 , H01L23/49811 , H01L2224/16 , H01L2224/16225 , H01L2924/01078 , H01L2924/01079 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/15312 , H05K3/325 , H05K7/1092 , H05K2201/10325 , H05K2201/10393 , H05K2201/10659 , H05K2201/10689 , H05K2201/10734 , Y10T29/4913
摘要： An electronic assembly includes one or more conductive clamps (302, 304, FIG. 3), which are used to supply current to an integrated circuit (IC) package (308). The conductive clamps are attached to a printed circuit (PC) board (312), which supplies the current to the IC package over one clamp, and receives returned current from the IC package over another clamp. Each clamp contacts a contact pad (330) on the surface of the PC board, and contacts another contact pad (334) on the top surface of the IC package. Vias (338, 339) and conductive planes (340, 342) within the package then carry current to and from an IC (e.g., IC 306) connected to the package. In another embodiment, the clamp (904, FIG. 9) holds a conductive structure (902) in place between the PC board contact pad (908) and the IC package contact pad (914), and current is carried primarily over the conductive structure, rather than over the clamp.
摘要翻译：电子组件包括用于向集成电路（IC）封装（308）提供电流的一个或多个导电钳位件（302,304，图3）。导电夹具连接到印刷电路板（PC）（312），该印刷电路板（312）通过一个夹具将电流提供给IC封装，并且通过另一个夹具接收来自IC封装的返回电流。每个夹具接触PC板表面上的接触焊盘（330），并接触IC封装顶表面上的另一接触焊盘（334）。封装内的通孔（338,339）和导电平面（340,342）然后将电流传送到连接到封装的IC（例如，IC 306）。在另一个实施例中，夹具（904，图9）将导电结构（902）保持在PC板接触焊盘（908）和IC封装接触焊盘（914）之间的适当位置，电流主要承载在导电结构，而不是超过钳位。

99. 发明申请

US20030103338A1 Electronic package having multiple-zone interconnects and methods of manufacture 有权
标题翻译：具有多区域互连的电子封装和制造方法
公开(公告)号：US20030103338A1
公开(公告)日：2003-06-05
申请号：US10004002
申请日：2001-11-30
申请人： Intel Corporation
发明人： Gilroy J. Vandentop , Yuan-Liang Li
IPC分类号： H05K007/10 , H05K007/12
CPC分类号： H01L24/73 , H01L23/49827 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/81801 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/30107 , H01L2924/351 , H05K3/3436 , H05K2201/10378 , H05K2201/10659 , Y02P70/613 , Y10T29/4913 , Y10T29/49144 , Y10T29/49169 , H01L2924/00
摘要： To accommodate thermal stresses arising from different coefficients of thermal expansion (CTE) of a packaged or unpackaged die and a substrate, the package incorporates two or more different interconnect zones. A first interconnect zone, located in a central region of the die, employs a relatively stiff interconnect structure. A second interconnect zone, located near the periphery of the die, employs a relatively compliant interconnect structure. Additional interconnect zones, situated between the first and second interconnect zones and having interconnect structure with compliance qualities intermediate those of the first and second zones, can optionally be employed. In one embodiment, solder connections providing low electrical resistance are used in the first interconnect zone, and compliant connections, such as nanosprings, are used in the second interconnect zone. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system are also described.
摘要翻译：为了适应由封装的或未封装的裸片和衬底的不同热膨胀系数（CTE）产生的热应力，封装包含两个或多个不同的互连区域。位于模具的中心区域中的第一互连区域采用相对较硬的互连结构。位于模具周边附近的第二互连区采用相对顺应的互连结构。位于第一和第二互连区之间并具有与第一和第二区之间的顺应性质量的互连结构的附加互连区可以任选地被采用。在一个实施例中，在第一互连区域中使用提供低电阻的焊接连接，并且在第二互连区域中使用诸如纳米脉冲的顺应连接。还描述了制造方法以及将包装应用于电子组件，电子系统和数据处理系统。

100. 发明授权

US06545868B1 Electronic module having canopy-type carriers 有权
公开(公告)号：US06545868B1
公开(公告)日：2003-04-08
申请号：US09688499
申请日：2000-10-16
申请人： Kenneth J. Kledzik , Jason C. Engle
发明人： Kenneth J. Kledzik , Jason C. Engle
IPC分类号： H05K720
CPC分类号： H05K1/141 , H01L25/105 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2225/1094 , H01L2924/0002 , H05K1/0231 , H05K3/0061 , H05K3/3405 , H05K3/3421 , H05K3/368 , H05K2201/049 , H05K2201/1034 , H05K2201/10515 , H05K2201/10659 , H05K2201/10689 , H05K2201/10734 , H05K2201/10924 , H01L2924/00
摘要： An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. A second primary embodiment of the invention utilizes a carrier substrate which has a pair of recesses for back-to-back surface mounting of the IC package pair. The two IC packages may be in contact with opposite sides of a heat sink layer embedded within the carrier substrate. Each resulting IC package unit is surface mounted to the main circuit board. A third primary embodiment of the invention incorporates features of both the first and second primary embodiments. One of the packages is mounted on a planar surface of the carrier right-side up, while the other package is mounted on the carrier in a recess upside down. Several variants of this embodiment are possible. Either the IC package that is mounted on the planar surface of the carrier, or the IC package that is mounted within the recess, may be mounted adjacent to the main circuit board. In the former case, the adjacent package of the package unit fits within a recess on the main circuit board. In the latter case, the adjacent package of the package unit mounts on a planar surface of the main circuit board. For any of the three primary main embodiments, the carrier may be equipped with its own set of interconnection leads which interface with the interconnection pads on the main circuit board or connection may be made directly between the leads of one package and the interconnection pads of the circuit board.

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