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91. 发明申请

US20060002498A1 CLOCK RECOVERY 有权
标题翻译：时钟恢复
公开(公告)号：US20060002498A1
公开(公告)日：2006-01-05
申请号：US11151560
申请日：2005-06-13
申请人： Andrew Pickering , Simon Forey , Robert Simpson , Shaun Lytollis
发明人： Andrew Pickering , Simon Forey , Robert Simpson , Shaun Lytollis
IPC分类号： H04L27/06
CPC分类号： H04L25/069 , H04L7/0025 , H04L7/0338
摘要： There is provided a Clock recovery apparatus comprising: an early/late voter for deciding whether a current sampling point needs to be advanced or retarded, wherein said early/late voter passes an Up/Down signal to an interpolator for maintaining a clock signal; a frequency accumulator and rate multiplier 30 for generating further signals which are summed with those of the Up/Down signal of the early/late voter to provide an improved control signal to the phase interpolator. The accumulator is responsive to frequency changes in the input signal, and said interpolator acts on said Up/Down signals to adjust the clock signal by stepping it forward or backward according to control need, so that said sampling point can be advanced or retarded.
摘要翻译：提供了一种时钟恢复装置，包括：早/晚选民，用于决定当前采样点是否需要提前或延迟，其中所述早/晚选民将向上/向下信号传递到内插器以维持时钟信号; 频率累积器和速率倍增器30，用于产生与早/晚选民的Up / Down信号相加的信号，以向相位插值器提供改进的控制信号。累加器响应于输入信号中的频率变化，并且所述内插器作用于所述上/下信号，以根据控制需要向前或向后逐步地调整时钟信号，使得所述采样点可以被提前或延迟。

92. 发明申请

US20050238120A1 Adaptable demodulator 有权
标题翻译：适应解调器
公开(公告)号：US20050238120A1
公开(公告)日：2005-10-27
申请号：US11111241
申请日：2005-04-21
申请人： Yveline Guilloux , Romain Palmade , Fabrice Romain , Sylvie Wuidart
发明人： Yveline Guilloux , Romain Palmade , Fabrice Romain , Sylvie Wuidart
IPC分类号： H04L27/06 , H03M1/12 , H04B1/59 , H04L25/06 , H04L25/49
CPC分类号： H04L27/06 , H04L25/069
摘要： A method and a circuit for detecting a binary state supported by an analog symbol, comprising sampling the symbol with a sampling signal based on a frequency having a period shorter than the duration of a symbol, selecting a number of significant samples smaller than the number of samples which would be obtained with a sampling of the symbol at said frequency, and deciding of the symbol state based on the selected samples.
摘要翻译：一种用于检测由模拟符号支持的二进制状态的方法和电路，包括基于具有比符号的持续时间短的周期的频率的采样信号对所述符号进行采样，选择少于所述符号的数量的有效样本数将利用所述频率处的符号采样获得的采样，以及基于所选择的采样来确定符号状态。

93. 发明授权

US06934324B2 Zero value-detecting circuit 失效
标题翻译：零值检测电路
公开(公告)号：US06934324B2
公开(公告)日：2005-08-23
申请号：US09934237
申请日：2001-08-21
申请人： Motohiro Yamazaki
发明人： Motohiro Yamazaki
IPC分类号： G11B20/10 , H03M3/02 , H04L25/06 , H04L25/00 , H04L27/00
CPC分类号： H04L25/069
摘要： Provided is a circuit that has a simple circuit configuration and can detect zero values in a 1-bit digital signal irrespective of a recording medium such as SACD. DSD data forming the 1-bit digital signal are successively sent to a shift register (1) whose number of stages corresponds to the number of bits of an idle pattern such as “101010101” which appears when assuming a zero value. For example, the shift register (1) is an 8-bit shift register. An adder (2) sums up the values at each stages of the shift register (1). A zero decision circuit (4) produces an output indicating decision of zero if the sum value is half of the number of bits. A counter (5) keeps counting while the output indicating zero decision is being delivered. If the count value of the counter exceeds a given value, the counter produces an output indicating detection of a zero value. In consequence, zero values in a 1-bit digital signal can be detected with a simple circuit configuration, regardless of the idle pattern that varies among different recording media such as SACDs.
摘要翻译：提供了具有简单的电路配置并且可以检测1位数字信号中的零值的电路，而不管诸如SACD的记录介质如何。形成1位数字信号的DSD数据被连续地发送到移位寄存器（1），移位寄存器（1）的级数对应于当假设为零值时出现的诸如“101010101”的空闲模式的位数。例如，移位寄存器（1）是8位移位寄存器。加法器（2）对移位寄存器（1）的各级的值求和。如果和值是位数的一半，则零判定电路（4）产生指示为零的输出的输出。计数器（5）在输出指示零决定被传递的同时继续计数。如果计数器的计数值超过给定值，则计数器产生一个表示检测到零值的输出。因此，无论在诸如SACD的不同记录介质中变化的空闲模式如何，都可以用简单的电路配置来检测1位数字信号中的零值。

94. 发明申请

US20040141567A1 Multi-level pulse amplitude modulation receiver 有权
标题翻译：多级脉冲幅度调制接收机
公开(公告)号：US20040141567A1
公开(公告)日：2004-07-22
申请号：US10348877
申请日：2003-01-22
发明人： Fuji Yang , Michael L. Craner
IPC分类号： H04L025/34 , H04L025/49 , H03K007/02 , H03K009/02
CPC分类号： H04L25/069 , H03L7/087 , H03L7/0891 , H03L7/091 , H04L7/033 , H04L25/066 , H04L25/4917
摘要： Multiple-level phase amplitude (M-PAM) clock and data recovery circuitry uses information from multiple phase detectors to generate one or more data sampling clocks that are optimized for each of the data slicers. One possible 4-PAM implementation includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The phase detector outputs are combined (e.g., via weighted voting, weighted average, minimum error, and/or minimum variance) to determine an optimized phase estimate for the clock used to sample the data at all three data slicers. Another 4-PAM implementation similarly includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The mid-amplitude edge slicer and phase detector are used in combination with the VCO to generate a central phase while a multiple-tap delay line provides N phase variants before and after the central phase. Information from the non-mid-amplitude edge slicers and phase detectors is used to choose a phase from among the phase variants that best suits the other data slicers. In yet another implementation, a single edge slicer, single phase detector, and single VCO is used to generate a key clock which is used by the edge slicer to track the symbol timing. A clock generator provides a single optimized clock (that is offset from the key clock) that is used by the data slicers. Bit error rates from the data slicers are used to adjust the offset until the data slicer clock is optimized with respect to all the slicers. Alternatively, multiple clocks are generated via offsets from the key clock, each being optimized to the data slicer group that it drives.
摘要翻译：多级相位幅度（M-PAM）时钟和数据恢复电路使用来自多个相位检测器的信息来生成为每个数据限幅器优化的一个或多个数据采样时钟。一个可能的4-PAM实现包括3个数据限幅器，3个边缘限幅器，3个相位检测器和一个VCO。相位检测器输出被组合（例如，经由加权投票，加权平均，最小误差和/或最小方差）以确定用于在所有三个数据限幅器上采样数据的时钟的优化相位估计。另一个4-PAM实现类似地包括3个数据限幅器，3个边缘限幅器，3个相位检测器和一个VCO。中间幅度边缘限幅器和相位检测器与VCO组合使用以产生中心相位，而多抽头延迟线在中心相之前和之后提供N相变量。来自非中间幅度边缘限幅器和相位检测器的信息用于从最适合其他数据限幅器的相位变量中选择一个相位。在又一实现中，使用单个边缘限幅器，单相检测器和单个VCO来产生密钥时钟，该时钟由边缘限幅器用于跟踪符号定时。时钟发生器提供由数据限幅器使用的单个优化时钟（偏离关键时钟）。来自数据限幅器的位错误率用于调整偏移量，直到相对于所有切片器优化数据切片器时钟。或者，通过来自键时钟的偏移产生多个时钟，每个时钟被优化为其驱动的数据限幅器组。

95. 发明申请

US20040066860A1 Passive redundant digital data receiver with dual comparator edge detection 失效
标题翻译：无源冗余数字数据接收机，具有双比较器边缘检测
公开(公告)号：US20040066860A1
公开(公告)日：2004-04-08
申请号：US10267438
申请日：2002-10-08
发明人： Karl Joseph Bois , David W. Quint , Randy K. Rannow
IPC分类号： H04L027/06
CPC分类号： H04L25/069
摘要： A passive coupling structure constructed using printed circuit board traces is used to separate the low and high frequency components of an incoming digital signal. The low and high frequency components of the signal are sent to separate receivers on an integrated circuit. The low frequency receiver may be a conventional level based receiver. The high frequency receiver is a Schmitt-trigger with hysteresis around a DC level or two comparators with separate reference voltages. The outputs of these receivers are combined to produce a receiver output that has increased reliability and noise immunity.
摘要翻译：使用印刷电路板迹线构建的无源耦合结构用于分离输入数字信号的低频和高频分量。信号的低频和高频分量被发送到集成电路上的分离接收器。低频接收机可以是基于传统级别的接收机。高频接收器是一个施密特触发器，具有直流电平周围的滞后或两个具有单独参考电压的比较器。这些接收机的输出被组合以产生具有增加的可靠性和抗噪声能力的接收器输出。

96. 发明申请

US20030202445A1 Data reproduction control method and apparatus, and optical disk unit 失效
标题翻译：数据再现控制方法和装置以及光盘单元
公开(公告)号：US20030202445A1
公开(公告)日：2003-10-30
申请号：US10457617
申请日：2003-06-09
申请人： Fujitsu Limited
发明人： Toru Fujiwara , Akira Nanba , Masakazu Taguchi
IPC分类号： G11B007/005
CPC分类号： G11B20/10212 , G11B20/10009 , G11B20/10046 , G11B20/10101 , G11B20/10481 , H03M13/41 , H03M13/6331 , H03M13/6343 , H03M13/6502 , H03M13/6577 , H04L25/062 , H04L25/069
摘要： The present invention realizes stable and more proper data reproduction even when a reproduced signal varies locally due to a noise or includes a steady distortion. In a data reproduction control method and apparatus, and an optical disk unit that adjust sampled values, in sampling a signal reproduced from a recording medium recorded with data, the frequencies of the levels of quantized data are counted, a histogram of the frequencies of the levels is created based on the counting results, and more accurate reproduced data is obtained by means of a distribution of the frequencies of the levels in the histogram.
摘要翻译：即使再现信号由于噪声而局部变化或包括稳定的失真，本发明实现了稳定和更合适的数据再现。在数据再现控制方法和装置以及调整采样值的光盘单元中，对从记录有数据的记录介质再现的信号进行采样时，对量化数据的电平的频率进行计数，基于计数结果创建电平，并且通过直方图中电平的频率的分布获得更准确的再现数据。

97. 发明申请

US20030198169A1 Data reproduction control method and apparatus, and optical disk unit 失效
公开(公告)号：US20030198169A1
公开(公告)日：2003-10-23
申请号：US10457758
申请日：2003-06-09
申请人： Fujitsu Limited
发明人： Toru Fujiwara , Akira Nanba , Masakazu Taguchi
IPC分类号： G11B007/005
CPC分类号： G11B20/10212 , G11B20/10009 , G11B20/10046 , G11B20/10101 , G11B20/10481 , H03M13/41 , H03M13/6331 , H03M13/6343 , H03M13/6502 , H03M13/6577 , H04L25/062 , H04L25/069
摘要： The present invention realizes stable and more proper data reproduction even when a reproduced signal varies locally due to a noise or includes a steady distortion. In a data reproduction control method and apparatus, and an optical disk unit that adjust sampled values, in sampling a signal reproduced from a recording medium recorded with data, the frequencies of the levels of quantized data are counted, a histogram of the frequencies of the levels is created based on the counting results, and more accurate reproduced data is obtained by means of a distribution of the frequencies of the levels in the histogram.

98. 发明授权

US06617917B2 Caller-ID demodulation apparatus and method using multiple thresholds 有权
公开(公告)号：US06617917B2
公开(公告)日：2003-09-09
申请号：US10086787
申请日：2002-03-01
申请人： Chung-gil Yang , Il-joong Kim
发明人： Chung-gil Yang , Il-joong Kim
IPC分类号： H03D300
CPC分类号： H04L7/0331 , H04L25/069 , H04L27/1563 , H04M1/573 , H04Q2213/13091 , H04Q2213/13199 , H04Q2213/13214 , H04Q2213/13216 , H04Q2213/1332 , H04Q2213/13322
摘要： A caller identification (ID) demodulating apparatus and method using multiple thresholds. An apparatus according to one embodiment comprises a zero crossing detector for generating pulses at points where the modulated caller ID information crosses zero and outputs each pulse as a zero crossing signal, a data extractor for computing a zero crossing interval between each output pulse of the zero crossing signal, and comparing the zero crossing interval with a plurality of thresholds to generate extracted data, and a clock generator for generating a data recovery clock signal for recovering the extracted data in response to the extracted data, wherein the data recovery clock signal is enabled at the middle point of the unit data length of the extracted data. The apparatus and method use multiple thresholds to extract data from caller ID modulated in a CPFSK format, thereby accurately extracting data at an interval where data “0” and “1” coexist. Furthermore, the clock signal for demodulating extracted data is generated about at the middle point of the unit data length of the extracted data, thereby demodulating data accurately.

99. 发明授权

US06522687B2 Data transmitter and receiver of a DS-CDMA communication system 有权
标题翻译： DS-CDMA通信系统的数据发射机和接收机
公开(公告)号：US06522687B2
公开(公告)日：2003-02-18
申请号：US09775600
申请日：2001-02-05
申请人： Jong-Hyeon Park , Je-Woo Kim
发明人： Jong-Hyeon Park , Je-Woo Kim
IPC分类号： H04B1500
CPC分类号： H04L25/069 , H04B1/707 , H04B2201/70701 , H04L27/206 , H04L27/2273
摘要： A data transmitter and receiver in a DS-CDMA communication system designed to prevent a serious amplitude shift in a transmission signal, facilitate recovery of data and clock signals and relieve the constraint of using a high linearity, high performance amplifier. The data transmitter includes a spread signal generating device, in which I-arm and Q-arm information signals of the first channel are spread by I-arm and Q-arm PN codes, respectively, and I-arm and Q-arm information signals of a predetermined number of following channels are spread by an inverted Q-arm PN code and the I-arm PN code, respectively. The data receiver includes a despread signal generating device, in which an I-arm despread signal is generated by multiplying I-arm and Q-arm digital baseband spread signals by I-arm and Q-arm PN codes, respectively, and adding the multiplication results, while a Q-arm despread signal is generated by multiplying Q-arm and I-arm digital baseband spread signal by an inverted I-arm PN code and the Q-arm PN code, respectively, and adding the multiplication results.
摘要翻译： DS-CDMA通信系统中的数据发射机和接收机，旨在防止传输信号的严重幅度偏移，便于恢复数据和时钟信号，并减轻使用高线性，高性能放大器的约束。数据发送器包括扩展信号发生装置，其中第一通道的I臂和Q臂信息信号分别由I臂和Q臂PN代码扩展，I臂和Q臂信息信号的预定数量的后续通道分别由反向Q臂PN码和I型PN码扩展。数据接收机包括解扩信号发生装置，其中分别通过I臂和Q臂数字基带扩展信号乘以I臂和Q-arm PN码产生I臂解扩信号，并且将乘法相加结果，通过将Q臂和I臂数字基带扩展信号分别乘以反相I臂PN码和Q-臂PN码分别产生Q臂解扩信号，并相加乘法结果。

100. 发明申请

US20020150172A1 Caller-ID demodulation apparatus and method using multiple thresholds 有权
标题翻译：来电显示解调装置和使用多个阈值的方法
公开(公告)号：US20020150172A1
公开(公告)日：2002-10-17
申请号：US10086787
申请日：2002-03-01
申请人： Samsung Electronics Co., Ltd.
发明人： Chung-Gil Yang , Il-Joong Kim
IPC分类号： H03D003/00
CPC分类号： H04L7/0331 , H04L25/069 , H04L27/1563 , H04M1/573 , H04Q2213/13091 , H04Q2213/13199 , H04Q2213/13214 , H04Q2213/13216 , H04Q2213/1332 , H04Q2213/13322
摘要： A caller identification (ID) demodulating apparatus and method using multiple thresholds. An apparatus according to one embodiment comprises a zero crossing detector for generating pulses at points where the modulated caller ID information crosses zero and outputs each pulse as a zero crossing signal, a data extractor for computing a zero crossing interval between each output pulse of the zero crossing signal, and comparing the zero crossing interval with a plurality of thresholds to generate extracted data, and a clock generator for generating a data recovery clock signal for recovering the extracted data in response to the extracted data, wherein the data recovery clock signal is enabled at the middle point of the unit data length of the extracted data. The apparatus and method use multiple thresholds to extract data from caller ID modulated in a CPFSK format, thereby accurately extracting data at an interval where data null0null and null1null coexist. Furthermore, the clock signal for demodulating extracted data is generated about at the middle point of the unit data length of the extracted data, thereby demodulating data accurately.
摘要翻译：一种使用多个阈值的呼叫者识别（ID）解调装置和方法。根据一个实施例的装置包括：零交叉检测器，用于在调制的呼叫者ID信息跨越零的点处产生脉冲，并且将每个脉冲作为零交叉信号输出;数据提取器，用于计算零点的每个输出脉冲之间的过零间隔交叉信号，并且将过零间隔与多个阈值进行比较以产生提取的数据;以及时钟发生器，用于响应于所提取的数据产生用于恢复提取的数据的数据恢复时钟信号，其中数据恢复时钟信号被使能在提取数据的单位数据长度的中点。该装置和方法使用多个阈值从CPFSK格式调制的呼叫者ID提取数据，从而以数据“0”和“1”共存的间隔精确地提取数据。此外，在提取的数据的单位数据长度的中点处产生用于解调提取的数据的时钟信号，从而精确地解调数据。

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