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91. 发明申请

US20040140830A1 Class AB digital to analog converter/line driver 失效
标题翻译： AB类数模转换器/线路驱动器
公开(公告)号：US20040140830A1
公开(公告)日：2004-07-22
申请号：US10720144
申请日：2003-11-25
申请人： Broadcom Corporation
发明人： Jan Mulder , Yee Ling Cheung
IPC分类号： H03K005/22
CPC分类号： H03K17/04106 , H03M1/146 , H03M1/204 , H03M1/365 , H03M1/742 , H04L25/026 , H04L25/0276
摘要： A differential line driver includes first, second, third and fourth cascode transistors connected in parallel, wherein drains of the first and third transistors are connected to a negative output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a positive output of the differential line driver. First, second, third and fourth switching transistors are connected in series with corresponding first, second, third and fourth cascode transistors and driven by a data signal. First and second compound transistors inputting a class AB operation signal at their gates, wherein the first compound transistor is connected to sources of the first and second switching transistors, and wherein the second compound transistor is connected to sources of the third and fourth switching transistors.
摘要翻译：差分线路驱动器包括并联连接的第一，第二，第三和第四共源共栅晶体管，其中第一和第三晶体管的漏极连接到差分线路驱动器的负输出，并且其中第二和第四晶体管的漏极连接到差分线路驱动器的正输出。第一，第二，第三和第四开关晶体管与对应的第一，第二，第三和第四共源共栅晶体管串联连接并由数据信号驱动。第一和第二复合晶体管在其栅极处输入AB类操作信号，其中第一复合晶体管连接到第一和第二开关晶体管的源极，并且其中第二复合晶体管连接到第三和第四开关晶体管的源极。

92. 发明授权

US06720798B2 Class AB digital to analog converter/line driver 失效
公开(公告)号：US06720798B2
公开(公告)日：2004-04-13
申请号：US10158193
申请日：2002-05-31
申请人： Jan Mulder , Yee Ling Cheung
发明人： Jan Mulder , Yee Ling Cheung
IPC分类号： H03K522
CPC分类号： H03K17/04106 , H03M1/146 , H03M1/204 , H03M1/365 , H03M1/742 , H04L25/026 , H04L25/0276
摘要： A differential line driver includes first, second, third and fourth cascode transistors connected in parallel, wherein drains of the first and third transistors are connected to a negative output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a positive output of the differential line driver. First, second, third and fourth switching transistors are connected in series with corresponding first, second, third and fourth cascode transistors and driven by a data signal. First and second compound transistors inputting a class AB operation signal at their gates, wherein the first compound transistor is connected to sources of the first and second switching transistors, and wherein the second compound transistor is connected to sources of the third and fourth switching transistors.

93. 发明授权

US06674388B2 High speed analog to digital converter 有权
标题翻译：高速模数转换器
公开(公告)号：US06674388B2
公开(公告)日：2004-01-06
申请号：US10349073
申请日：2003-01-23
申请人： Jan Mulder
发明人： Jan Mulder
IPC分类号： H03M114
CPC分类号： H03M1/0863 , H03K17/04106 , H03M1/146 , H03M1/204 , H03M1/36 , H03M1/365
摘要： An analog to digital converter includes a reference ladder, a track-and-hold amplifier tracking an input signal with its output signal during the phase &phgr;1 and holding a sampled value during, a coarse analog to digital converter having a plurality of coarse amplifiers each inputting a corresponding tap from the reference ladder and the output signal, a fine analog-to-digital converter having a plurality of fine amplifiers inputting corresponding taps from the reference ladder and the output signal, the taps selected based on outputs of the coarse amplifiers, a clock having phases &phgr;1 and &phgr;2, a circuit responsive to the clock that receives the output signal, the circuit substantially passing the output signal and the corresponding taps to the fine amplifiers during the phase &phgr;2 and substantially rejecting the output signal and the corresponding taps during the phase &phgr;1, and an encoder converting outputs of the coarse and fine amplifiers to an N-bit digital signal representing the input signal.
摘要翻译：模数转换器包括参考梯形图，跟踪和保持放大器，在相位phi1期间跟踪具有其输出信号的输入信号并保持采样值，粗略模数转换器具有多个粗放大器，每个粗放大器输入来自参考梯形图和输出信号的对应抽头，具有多个精细放大器的精细模数转换器，该精细放大器从参考梯形图输入相应的抽头和输出信号，基于粗放大器的输出选择的抽头，具有相位phi1和phi2的时钟，响应于接收输出信号的时钟的电路，电路在相位phi2期间基本上将输出信号和相应的抽头传递到精细放大器，并在该期间基本上拒绝输出信号和对应的抽头相位phi1和将粗略和精细放大器的输出转换成表示th的N位数字信号的编码器 e输入信号。

94. 发明申请

US20030234735A1 ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：模拟数字转换器
公开(公告)号：US20030234735A1
公开(公告)日：2003-12-25
申请号：US10176695
申请日：2002-06-20
发明人： Robert William Kressin
IPC分类号： H03M001/12 , H03M001/34
CPC分类号： H03M1/146 , H03M1/365
摘要： Disclosed herein is an analog-to-digital converter having first and second comparator stages, a voltage reference stage, a switching stage, and an encoder. The first comparator stage receives an analog signal and a threshold and outputs a control signal. The voltage reference stage receives the control signal and outputs one of two or more sets of reference voltages. The second comparator stage receives the analog signal, as well as the set of reference voltages output from the voltage reference stage, and outputs a thermometer code in response to comparisons of the analog signal to the reference voltages. The switching stage receives the control signal, and in response thereto, variously couples inputs of the encoder to: bits of the thermometer code output from the second comparator stage, a first potential, or a second potential. Methods for converting analog signals to digital signals are also disclosed.
摘要翻译：这里公开了具有第一和第二比较器级，电压基准级，开关级和编码器的模拟 - 数字转换器。第一比较器级接收模拟信号和阈值并输出控制信号。电压基准级接收控制信号并输出两组或更多组参考电压之一。第二比较器级接收模拟信号以及从电压基准级输出的一组参考电压，并且响应于模拟信号与参考电压的比较而输出温度计代码。开关级接收控制信号，并且响应于此，将编码器的输入端各种耦合到从第二比较器级输出的温度计代码的位，第一电位或第二电位。还公开了将模拟信号转换为数字信号的方法。

95. 发明授权

US06664910B1 Distributed averaging analog to digital converter topology 有权
公开(公告)号：US06664910B1
公开(公告)日：2003-12-16
申请号：US10460622
申请日：2003-06-13
申请人： Jan Mulder , Christopher Michael Ward
发明人： Jan Mulder , Christopher Michael Ward
IPC分类号： H03M112
CPC分类号： H03K17/04106 , H03M1/0646 , H03M1/146 , H03M1/204 , H03M1/206 , H03M1/361 , H03M1/365
摘要： An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

96. 发明申请

US20030218560A1 DISTRIBUTED AVERAGING ANALOG TO DIGITAL CONVERTER TOPOLOGY 有权
标题翻译：分布式平均模拟到数字转换器拓扑学
公开(公告)号：US20030218560A1
公开(公告)日：2003-11-27
申请号：US10460622
申请日：2003-06-13
申请人： Broadcom Corporation
发明人： Jan Mulder , Christopher Michael Ward
IPC分类号： H03M001/36
CPC分类号： H03K17/04106 , H03M1/0646 , H03M1/146 , H03M1/204 , H03M1/206 , H03M1/361 , H03M1/365
摘要： An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.
摘要翻译：模数转换器包括连接到参考梯形图的抽头的第一放大器阵列，第二放大器阵列，其中第一放大器阵列中的每个放大器仅连接到第二放大器阵列的两个放大器，第三放大器阵列，其中每个第二放大器阵列中的放大器仅连接到第三放大器阵列的两个放大器，以及连接到第三放大器阵列的输出的编码器，其将输出转换为N位数字信号。

97. 发明授权

US06653966B1 Subranging analog to digital converter with multi-phase clock timing 有权
标题翻译：使用多相时钟定时将模数转换器分段
公开(公告)号：US06653966B1
公开(公告)日：2003-11-25
申请号：US10359201
申请日：2003-02-06
申请人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
IPC分类号： H03M100
CPC分类号： H03M1/146 , H03K17/04106 , H03M1/204 , H03M1/365
摘要： An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
摘要翻译： N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

98. 发明授权

US6091346A Multi-flash analog to digital converter using floating voltages 失效
标题翻译：使用浮动电压的多闪光模数转换器
公开(公告)号：US6091346A
公开(公告)日：2000-07-18
申请号：US461149
申请日：1995-06-05
申请人： David Muresan , David D. Muresan
发明人： David Muresan , David D. Muresan
IPC分类号： H03M1/14 , H03M1/12
CPC分类号： H03M1/146
摘要： A high resolution multi-flash analog-to-digital converter comprised of multiple small resolution full-flash analog-to-digital converters combined in such a manner as to generate a higher resolution digital voltage. The first small resolution analog-to-digital flash converter will generate the lowest order bits of the multi-flash analog-to-digital converter. The second small resolution analog-to-digital flash converter will generate the next higher order bits of the multi-flash analog-to-digital converter, and so on, until the last small resolution analog-to-digital flash converter will generate the most significant order bits of the multi-flash analog-to-digital converter.
摘要翻译：由多个小分辨率全闪存模数转换器组成的高分辨率多闪光模数转换器组合在一起，以产生更高分辨率的数字电压。第一个小分辨率模数转换器将产生多闪光模数转换器的最低位。第二个小分辨率模数转换器将产生多闪光模数转换器的下一个较高位，等等，直到最后一个小分辨率的模数转换器将产生最多多闪光模数转换器的重要顺序位。

99. 发明授权

US6025794A Signal transmission circuit, signal transmission method A/D converter and solid-state imaging element 失效
标题翻译：信号传输电路，信号传输方式A / D转换器和固态成像元件
公开(公告)号：US6025794A
公开(公告)日：2000-02-15
申请号：US792769
申请日：1997-02-03
申请人： Keiichi Kusumoto , Akira Matsuzawa , Kenji Murata , Youichi Okamoto
发明人： Keiichi Kusumoto , Akira Matsuzawa , Kenji Murata , Youichi Okamoto
IPC分类号： H03M1/12 , H03M1/14 , H03M1/36
CPC分类号： H03M1/1245 , H03M1/146 , H03M1/204 , H03M1/365
摘要： According to the present invention, a signal transmission circuit for receiving an input signal and outputting an output signal corresponding to the input signal is provided. The signal transmission circuit includes: a first capacitance; an electric charge supply section for supplying electric charge corresponding to the input signal to the first capacitance; a second capacitance; and a transfer section for transferring the electric charge from the first capacitance to the second capacitance. In the signal transmission circuit, the second capacitance is larger than the first capacitance.
摘要翻译：根据本发明，提供一种用于接收输入信号并输出与输入信号对应的输出信号的信号传输电路。信号传输电路包括：第一电容; 电荷供给部，用于将对应于所述输入信号的电荷提供给所述第一电容; 第二电容; 以及用于将电荷从第一电容转移到第二电容的转移部分。在信号传输电路中，第二电容大于第一电容。

100. 发明授权

US5459465A Sub-ranging analog-to-digital converter 失效
标题翻译：子范围模数转换器
公开(公告)号：US5459465A
公开(公告)日：1995-10-17
申请号：US140675
申请日：1993-10-21
申请人： Mark R. Kagey
发明人： Mark R. Kagey
IPC分类号： H03M1/14 , H03M1/36 , H03M1/20
CPC分类号： H03M1/146 , H03M1/365
摘要： The present invention provides a sub-ranging analog-to-digital (A/D) converter with improved speed and power consumption characteristics relative to known sub-ranging converters. The sub-ranging A/D converter utilizes information relating to the values of the bits determined in one stage to define the range of operation for a subsequent stage. In one embodiment, the subsequent stage utilizes three-input comparators in determining the value of a bit. Two of the inputs are used to receive signals representative of the upper and lower limits of the range of operation that has been determined by the prior stage and the other input is used to receive the analog signal. The three-input comparator operates to produce an output signal that is indicative of the relationship of the analog signal to a threshold level within the defined range of operation determined by the prior stage.
摘要翻译：本发明提供了一种相对于已知子范围转换器具有改进的速度和功耗特性的子范围模数（A / D）转换器。子范围A / D转换器利用与一级中确定的位的值有关的信息来定义后续级的操作范围。在一个实施例中，后续级利用三输入比较器来确定位的值。两个输入用于接收表示由前一级确定的操作范围的上限和下限的信号，另一个输入用于接收模拟信号。三输入比较器操作以产生一个输出信号，该输出信号指示模拟信号与在前一阶段确定的确定的操作范围内的阈值水平的关系。

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