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91. 发明授权

US08253436B2 Semiconductor integrated circuit with data transmitting and receiving circuits 失效
标题翻译：具有数据发射和接收电路的半导体集成电路
公开(公告)号：US08253436B2
公开(公告)日：2012-08-28
申请号：US12876760
申请日：2010-09-07
申请人： Masayasu Komyo , Yoichi Iizuka
发明人： Masayasu Komyo , Yoichi Iizuka
IPC分类号： H03K17/16 , H03K19/003 , G06F13/42
CPC分类号： H03K19/00361 , G11C7/1006 , G11C14/0009 , H03K19/0005 , H03K19/00315
摘要： Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.
摘要翻译：提供了根据本发明的示例性方面的半导体集成电路，包括数据发送电路和数据接收电路，其接收从数据发送电路发送的数据。数据发送电路包括输出数据或将输出设置为高阻抗状态的数据输出电路和向数据输出电路输出控制信号的控制电路，使得数据输出电路在数据发送时输出数据在数据发送电路在发送数据之后进一步发送另一数据时，数据输出电路在先前的数据传输之后的预定时段期间，数据输出电路继续输出上一次数据传输中的数据。

92. 发明申请

US20120134060A1 ELECTRONIC DEVICE WITH PROTECTION CIRCUIT 有权
标题翻译：具有保护电路的电子设备
公开(公告)号：US20120134060A1
公开(公告)日：2012-05-31
申请号：US13389179
申请日：2009-08-06
申请人： Hubert Bode , Mauro Giacomini
发明人： Hubert Bode , Mauro Giacomini
IPC分类号： H02H9/02
CPC分类号： H01L27/0285 , H03K19/00315
摘要： An electronic device comprises an application circuit; a first supply rail having a first electric potential; a second supply rail having a second electric potential different from the first electric potential; at least one terminal having a third electric potential, connected to the application circuit; and a protection circuit for protecting the application circuit from an injected current. The protection circuit comprises a first conductive line connected between the at least one terminal and the first supply rail, the first conductive line comprising a first switch having a first control input; and a first voltage amplifier circuit having a first input connected to the at least one terminal, a second input connected to the second supply rail and a first output connected to the first control input.
摘要翻译：电子设备包括应用电路; 具有第一电位的第一供电轨; 具有不同于第一电位的第二电位的第二供电轨; 具有第三电位的至少一个端子，连接到所述应用电路; 以及用于保护施加电路免受注入电流的保护电路。所述保护电路包括连接在所述至少一个端子和所述第一电源轨之间的第一导线，所述第一导线包括具有第一控制输入的第一开关; 以及第一电压放大器电路，其具有连接到所述至少一个端子的第一输入端，连接到所述第二电源轨道的第二输入端和连接到所述第一控制输入端的第一输出端。

93. 发明授权

US08106699B2 High signal level compliant input/output circuits 有权
标题翻译：高信号电平兼容输入/输出电路
公开(公告)号：US08106699B2
公开(公告)日：2012-01-31
申请号：US12181645
申请日：2008-07-29
申请人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
发明人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
IPC分类号： H03L5/00
CPC分类号： H03K19/00315 , H03K19/018507
摘要： A level shifter has at least one of either a pull up or a pull down circuit. The circuit is made of electronic components with reliability limits less than a maximum signal level output by the level shifter. The level shifter also has a timing circuit coupled to at least on of either the pull up or pull down circuit. The timing circuit controls a time of application of an input signal to at least one of either the pull up or pull down circuit preventing a terminal to terminal signal level experienced by the electronic components exceeding the reliability limits.
摘要翻译：电平移位器具有上拉或下拉电路中的至少一个。该电路由可靠性限制小于电平转换器输出的最大信号电平的电子元件组成。电平移位器还具有耦合到上拉或下拉电路中的至少一个的定时电路。定时电路控制将输入信号施加到上拉或下拉电路中的至少一个的时间，以防止电子部件经受的终端信号电平超过可靠性限制。

94. 发明申请

US20110316505A1 Output Buffer With Improved Output Signal Quality 审中-公开
标题翻译：输出缓冲器具有改善的输出信号质量
公开(公告)号：US20110316505A1
公开(公告)日：2011-12-29
申请号：US12821168
申请日：2010-06-23
申请人： Aatmesh Shrivastava
发明人： Aatmesh Shrivastava
IPC分类号： G05F1/10
CPC分类号： H03K19/00315 , H03K19/018521
摘要： An output buffer receives an input signal and generates an output signal at an output node. The output buffer contains a driver circuit. The driver circuit includes two pairs of cascoded transistors connected at a junction node. Each of the cascoded pairs receives a corresponding level-shifted signal representing the input signal, and generates corresponding driver signals on driver nodes which are coupled to the output node. The driver circuit includes a capacitor connected between one of the driver nodes and the junction node. The capacitor enables the corresponding driver signal to be generated to reach a desired voltage quickly. The output impedance of the output buffer with which the output signal is launched is reduced and more closely matched the impedance of the path on which the output signal is provided. Signal quality of the output signal is thereby improved.
摘要翻译：输出缓冲器接收输入信号并在输出节点产生输出信号。输出缓冲器包含驱动电路。驱动器电路包括连接在连接节点处的两对级联晶体管。每个级联对接收表示输入信号的对应的电平移位信号，并且在耦合到输出节点的驱动器节点上产生相应的驱动器信号。驱动器电路包括连接在其中一个驱动器节点和连接节点之间的电容器。该电容使得可以产生相应的驱动器信号以快速达到所需电压。输出信号被输出的输出缓冲器的输出阻抗减小并且与提供输出信号的路径的阻抗更紧密地匹配。从而提高输出信号的信号质量。

95. 发明授权

US08072720B2 Electrostatic protection circuit 有权
标题翻译：静电保护电路
公开(公告)号：US08072720B2
公开(公告)日：2011-12-06
申请号：US12078977
申请日：2008-04-09
申请人： Mototsugu Okushima
发明人： Mototsugu Okushima
IPC分类号： H02H9/00
CPC分类号： H03K19/00315 , H01L27/0266 , H03K17/08104
摘要： An electrostatic protection circuit that affords protection without effecting transfer of an ordinary output signal includes an output terminal; a ground terminal; a first N-channel transistor having its drain and source connected between the output terminal and the ground terminal GND; a first electrostatic protection element connecting the output terminal and the ground terminal; and a second electrostatic protection element connected the drain and gate of the first N-channel transistor. The second N-channel transistor is connected to the gate of the first N-channel transistor. The gate potential of the first N-channel transistor rises and the gate-to-drain voltage of the first N-channel transistor is limited to a value below a prescribed value by a current that flows into the second electrostatic protection element owing to application of static electricity to the output terminal, and resistance of the second N-channel transistor, which is the ON state, as seen from the gate of the first N-channel transistor.
摘要翻译：提供保护而不影响普通输出信号的传输的静电保护电路包括输出端子; 地面终端; 第一N沟道晶体管，其漏极和源极连接在输出端和接地端GND之间; 连接输出端子和接地端子的第一静电保护元件; 以及连接第一N沟道晶体管的漏极和栅极的第二静电保护元件。第二N沟道晶体管连接到第一N沟道晶体管的栅极。第一N沟道晶体管的栅极电位上升，第一N沟道晶体管的栅极至漏极电压由于施加到第二静电保护元件的电流而被限制在低于规定值的值从第一N沟道晶体管的栅极看到的是输出端子的静电和作为导通状态的第二N沟道晶体管的电阻。

96. 发明申请

US20110260785A1 Low Leakage and Data Retention Circuitry 有权
标题翻译：低泄漏和数据保留电路
公开(公告)号：US20110260785A1
公开(公告)日：2011-10-27
申请号：US13074291
申请日：2011-03-29
申请人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
发明人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
IPC分类号： G05F1/10
CPC分类号： H03K19/0016 , G11C5/14 , G11C5/144 , G11C5/148 , H02M3/07 , H03K3/0372 , H03K3/356086 , H03K3/356113 , H03K5/14 , H03K17/102 , H03K19/00315
摘要： An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
摘要翻译：集成电路包括第一电路和睡眠晶体管电路。第一个电路接收输入信号并处理输入信号。第一电路还保持具有低泄漏的睡眠状态的数据。睡眠晶体管电路耦合到第一电路并且接收具有负电压的睡眠信号。休眠电路降低处于休眠状态的第一电路的功耗，以便在将数据保留在第一电路中的同时基于睡眠信号具有低泄漏。

97. 发明授权

US08035410B2 Latch circuit 有权
标题翻译：锁存电路
公开(公告)号：US08035410B2
公开(公告)日：2011-10-11
申请号：US12878532
申请日：2010-09-09
申请人： Taiki Uemura , Yoshiharu Tosaka
发明人： Taiki Uemura , Yoshiharu Tosaka
IPC分类号： H03K19/003
CPC分类号： H03K19/003 , H03K3/356156 , H03K19/00315 , H03K19/0033
摘要： A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.
摘要翻译：锁存电路包括具有反相器电路和至少两个输入端子的反馈电路和用于将与输入信号具有相同相位的输入信号或与时钟信号同步的反馈电路的输入端子的信号输入的输入电路。在反馈电路部分中，仅当输入信号或具有与输入信号相同相位的信号同时输入到至少两个输入端时，使用预定数量的放大级的正反馈被施加到输入终端。

98. 发明申请

US20110193588A1 MULTI-MODE CIRCUIT AND A METHOD FOR PREVENTING DEGRADATION IN THE MULTI-MODE CIRCUIT 有权
标题翻译：多模式电路和多模电路中防止降级的方法
公开(公告)号：US20110193588A1
公开(公告)日：2011-08-11
申请号：US12703793
申请日：2010-02-11
申请人： Palkesh JAIN , Nagaraj Savithri , Usha Narasimha
发明人： Palkesh JAIN , Nagaraj Savithri , Usha Narasimha
IPC分类号： H03K19/003 , H03K19/096
CPC分类号： H03K19/00315 , G06F1/10 , H03K5/135 , H03K5/1504
摘要： Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is responsive to a first signal to become inactive when the circuit enters into a second mode, thereby preventing degradation of the first transistor when the circuit enters into the second mode. A second transistor is coupled to the first transistor. The second transistor is responsive to a second signal to generate a third signal. A third transistor is coupled to the second transistor. The third transistor is responsive to the third signal to become inactive when the circuit enters into the second mode, thereby preventing degradation of the third transistor when the circuit enters into the second mode.
摘要翻译：多模电路（电路）和防止电路劣化的方法。电路包括第一晶体管，其使第一模式中的电路起作用。当电路进入第二模式时，第一晶体管响应于第一信号变为无效，从而防止当电路进入第二模式时第一晶体管的劣化。第二晶体管耦合到第一晶体管。第二晶体管响应于第二信号以产生第三信号。第三晶体管耦合到第二晶体管。当电路进入第二模式时，第三晶体管响应于第三信号变为无效，从而防止当电路进入第二模式时第三晶体管的劣化。

99. 发明授权

US07906988B2 Tolerant buffer circuit and interface 有权
标题翻译：宽容缓冲电路和接口
公开(公告)号：US07906988B2
公开(公告)日：2011-03-15
申请号：US12621776
申请日：2009-11-19
申请人： Kazuyo Ohta , Hideyuki Kihara
发明人： Kazuyo Ohta , Hideyuki Kihara
IPC分类号： H03K19/00 , H03K19/02
CPC分类号： H03K17/08142 , H03K19/00315
摘要： The tolerant buffer circuit and interface are provided in which reverse inflow of current to a power supply voltage from an output terminal does not occur, even if the output terminal is at a higher potential than an output circuit power supply voltage during open-drain operation in an output circuit of a semiconductor integrated circuit, or if the output circuit power supply voltage becomes 0 V. A tolerant buffer circuit is provided with first and second PMOS transistors that are connected in series and that share a source between a power supply terminal and an output terminal, an NMOS transistor connected between the output terminal and a ground terminal, a first inverter output-connected to the gate of the first PMOS transistor, a second inverter output-connected to the gate of the second PMOS transistor, and a control circuit that outputs first, second, and third control signals to the first PMOS transistor, the second PMOS transistor, and the NMOS transistor, respectively, and controls the on/off state of these MOS transistors.
摘要翻译：提供了容限缓冲电路和接口，其中即使输出端子比开漏运行期间的输出电路电源电压高的电位，也不会发生电流与输出端子的电源电压的反向流入半导体集成电路的输出电路，或者输出电路电源电压为0V。容限缓冲电路设置有串联连接的第一和第二PMOS晶体管，并且在电源端子和输出端子，连接在输出端子和接地端子之间的NMOS晶体管，输出连接到第一PMOS晶体管的栅极的第一反相器，输出连接到第二PMOS晶体管的栅极的第二反相器，以及控制电路其分别将第一，第二和第三控制信号输出到第一PMOS晶体管，第二PMOS晶体管和NMOS晶体管，并且con 控制这些MOS晶体管的开/关状态。

100. 发明申请

US20110057721A1 SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路
公开(公告)号：US20110057721A1
公开(公告)日：2011-03-10
申请号：US12876760
申请日：2010-09-07
申请人： Masayasu KOMYO , Yoichi IIZUKA
发明人： Masayasu KOMYO , Yoichi IIZUKA
IPC分类号： H04B1/10 , H03K17/00
CPC分类号： H03K19/00361 , G11C7/1006 , G11C14/0009 , H03K19/0005 , H03K19/00315
摘要： Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.
摘要翻译：提供了根据本发明的示例性方面的半导体集成电路，包括数据发送电路和数据接收电路，其接收从数据发送电路发送的数据。数据发送电路包括输出数据或将输出设置为高阻抗状态的数据输出电路和向数据输出电路输出控制信号的控制电路，使得数据输出电路在数据发送时输出数据在数据发送电路在发送数据之后进一步发送另一数据时，数据输出电路在先前的数据传输之后的预定时段期间，数据输出电路继续输出上一次数据传输中的数据。

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