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91. 发明授权

US5027423A Image-processing integrated circuit device 失效
标题翻译：图像处理集成电路器件
公开(公告)号：US5027423A
公开(公告)日：1991-06-25
申请号：US378543
申请日：1989-07-12
申请人： Tetsuro Kawata , Eiri Hashimoto , Nobuaki Miyakawa
发明人： Tetsuro Kawata , Eiri Hashimoto , Nobuaki Miyakawa
IPC分类号： H04N1/409 , G06T5/20 , H03H17/02
CPC分类号： H03H17/0202
摘要： An image-processing integrated circuit device comprises a delay circuit and adder group, a multiplication block group, and an adder group. Image data in a window are fed to the delay circuit and adder group simultaneously row by row and then added up for every symmetrical positions in the window. The respective sums of the image data thus added up for every symmetrical positions are multiplied by corresponding coefficient data in the multiplication block group. Lastly, the respective results of multiplication obtained from the multiplication block group are added up by the adder group to thereby obtain a filter output. The delay circuit and adder group, the multiplication block group, and the adder group can be integrated to form one image-processing integrated circuit device. Accordingly, the number of parts is reduced. Further, not only the image data can be fed into the delay circuit and adder group simultaneously but also the multiplication in the multiplication block group can be carried out in parallel and simultaneously by using exclusive multiplication blocks each provided for symmetrical positions in the window. Accordingly, the speed in filtering processing becomes high.
摘要翻译：图像处理集成电路装置包括延迟电路和加法器组，乘法块组和加法器组。窗口中的图像数据逐行地馈送到延迟电路和加法器组，然后对于窗口中的每个对称位置相加。对于每个对称位置，这样相加的图像数据的各个和乘以乘法块组中的对应系数数据。最后，由加法器组相加从乘积组获得的相乘乘法结果，从而获得滤波器输出。延迟电路和加法器组，乘法块组和加法器组可以集成形成一个图像处理集成电路器件。因此，部件的数量减少。此外，不仅可以将图像数据同时馈送到延迟电路和加法器组，而且还可以并行地并行地通过使用为窗口中的对称位置提供的专用乘法块来执行乘法器组中的乘法。因此，滤波处理的速度变高。

92. 发明授权

US5016207A High-speed digital filter processor including parallel paths for processing data, suitable for use in spatial filter image processing 失效
标题翻译：高速数字滤波处理器包括用于处理数据的并行路径，适用于空间滤波图像处理
公开(公告)号：US5016207A
公开(公告)日：1991-05-14
申请号：US503424
申请日：1990-04-03
申请人： Tatsuya Fujii , Yutaka Sato , Masafumi Tanaka
发明人： Tatsuya Fujii , Yutaka Sato , Masafumi Tanaka
IPC分类号： H04N1/409 , G06T5/20 , H03H17/02
CPC分类号： H03H17/0202
摘要： A digital filter processor includes an input part for distributing an input digital data train including a plurality of digital data to a plurality of systems. Each of the systems is provided with a corresopnding one of the distributed data trains at the same time. Each of the systems includes an operation part for multiplying each digital data included in the corresponding one of the distributed data trains by a corresponding multiplication factor at the same time to thereby generate multiplied data and for generating a sum signal indicative of a sum total of the multiplied data related to the corresponding one of the distributed data trains, each of the systems outputting the sum signal at the same time. The operation part also includes a selection part for selecting one of the sum signals supplied from the operation parts provided for the plurality of systems and for outputting an output digital signal.
摘要翻译：数字滤波处理器包括用于将包括多个数字数据的输入数字数据串分配到多个系统的输入部分。每个系统同时具有相应的分布式数据列。每个系统包括操作部分，用于将分布式数据列中的相应一个分配数据列中包含的每个数字数据同时乘以相应的乘法因子，从而产生相乘的数据，并产生一个和信号，该和信号表示与相应的一个分布式数据列有关的相乘数据，每个系统同时输出和信号。操作部还包括选择部，用于选择从为多个系统提供的操作部分提供的和信号中的一个，并输出输出数字信号。

93. 发明授权

US4862403A Digital filter 失效
标题翻译：数字滤波器
公开(公告)号：US4862403A
公开(公告)日：1989-08-29
申请号：US797845
申请日：1985-11-14
申请人： Seiichiro Iwase , Takao Yamazaki
发明人： Seiichiro Iwase , Takao Yamazaki
IPC分类号： H04N5/21 , H03H17/02 , H03H17/06
CPC分类号： H03H17/0202
摘要： A digital filter has an input terminal provided with an input digital signal. A delay circuit connected to the input terminal produces a plurality of delayed digital signals each having a different delay time with respect to the input digital signal. A first circuit adds the input digital signal and/or the plurality of delayed digital signals to one or more digital coefficient signals of the same value so as to produce one or more added digital signals. A circuit multiplies the one or more respective digital coefficient signals by the one or more added digital signals and/or one or more of the plurality of delayed digital signals to produce a plurality of multiplied digital signals. A second circuit adds the plurality of multiplied digital signals to produce an output digital signal, and a circuit connected between the delay circuit and a multiplying circuit increases the one or more added digital signals and/or the one or more of the plurality of delayed digital signals by one or more predetermined numbers of times, whereby the one or more respective digital coefficient signals have inversely proportional values corresponding to the one or more predetermined numbers of times of the values of the one or more added digital signals and/or the one or more of the plurality of delayed digital signals.
摘要翻译：数字滤波器具有设置有输入数字信号的输入端。连接到输入端的延迟电路产生多个相对于输入数字信号具有不同延迟时间的延迟数字信号。第一电路将输入数字信号和/或多个延迟的数字信号添加到相同值的一个或多个数字系数信号，以便产生一个或多个相加的数字信号。一个电路将一个或多个相应的数字系数信号乘以一个或多个相加的数字信号和/或多个延迟的数字信号中的一个或多个，以产生多个相乘的数字信号。第二电路将多个相乘的数字信号相加以产生输出数字信号，并且连接在延迟电路和乘法电路之间的电路增加一个或多个相加的数字信号和/或多个延迟数字信号中的一个或多个一个或多个预定次数的信号，由此一个或多个相应的数字系数信号具有对应于一个或多个相加数字信号的值的一个或多个预定次数的反比例值和/或一个或多个更多的多个延迟数字信号。

94. 发明授权

US4821223A Two-dimensional finite impulse response filters 失效
标题翻译：二维有限脉冲响应滤波器
公开(公告)号：US4821223A
公开(公告)日：1989-04-11
申请号：US910523
申请日：1986-09-23
申请人： Morgan W. A. David
发明人： Morgan W. A. David
IPC分类号： H03H17/06 , H03H17/02 , G06F15/31
CPC分类号： H03H17/0202
摘要： A two-dimensional finite impulse response (FIR) filter comprises a demultiplexer for demultiplexing an input data signal comprising adjacent digital words into p (e.g. 2) slower data signals each having a slower rate equal to 1/p (e.g. 1/2) of the data rate of the input signal and each comprising every p.sup.th (e.g. every alternate) word of the input signal. The slower data signals are passed to p (e.g. 2) filter portions each comprising a horizontal FIR filter and a vertical FIR filter. The horizontal filters are each connected to receive all of the slower data signals and all of them are operative simultaneously to effect horizontal filtration by periodically processing sets of adjacent words of the input signal, the sets of adjacent words being processed at any one time by the respective horizontal filters being offset with respect to one another by one word. A multiplexer receives output signals of the filter portions to form a filtered output data signal having a data rate equal to that of the input data signal.
摘要翻译：二维有限脉冲响应（FIR）滤波器包括解复用器，用于将包括相邻数字字的输入数据信号解复用为p（例如2）慢速数据信号，每个慢速数据信号具有等于1 / p（例如1/2）输入信号的数据速率，每个包括输入信号的每pth（例如每个交替）字。较慢的数据信号被传递到每个包括水平FIR滤波器和垂直FIR滤波器的p（例如2）滤波器部分。水平滤波器各自被连接以接收所有较慢的数据信号，并且它们都可同时工作以通过周期性地处理输入信号的相邻字的集合来实现水平滤波，相邻字的集合在任何时间被相应的水平滤波器相对于彼此偏移一个字。多路复用器接收滤波器部分的输出信号以形成数据速率等于输入数据信号的数据速率的滤波输出数据信号。

95. 发明授权

US4805129A Two-dimensional finite impulse response filter arrangements 失效
标题翻译：二维有限脉冲响应滤波器布置
公开(公告)号：US4805129A
公开(公告)日：1989-02-14
申请号：US110452
申请日：1987-10-20
申请人： Morgan W. A. David
发明人： Morgan W. A. David
IPC分类号： H03H17/02 , G06K9/40
CPC分类号： H03H17/0202
摘要： A two-dimensional finite impulse response filter arrangement for filtering a signal which represents an image and which comprises a sequence of digital words comprises a two-dimensional finite impulse response filter operative during each of a plurality of successive clock periods to effect filtration over a predetermined area of the image by multiplying each of a set of the digital words in a spatial array by a respective weighting coefficient in a corresponding set of weighting coefficients, and summing the resulting products to produce therefrom an output filtered digital word. The filter includes a store storing weighting coefficient data defining a profile which when rotated about an axis generates a three-dimensional representation of the values of weighting coefficients corresponding to a required two-dimensional response characteristic of the filter, first calculating means operative in response to each of the digital words to calculate the radius from the axis of the position of the corresponding weighting coefficient in the representation, whereby the value of the respective weighting coefficient corresponding to each of the positions in the array can be derived from the store in dependence on the value of the corresponding radius, and second calculating means to multiply each digital word by the respective weighting coefficient of the corresponding set of weighting coefficients, and to sum the resulting products to derive the required output filtered digital word.
摘要翻译：用于对表示图像的信号进行滤波并且包括数字字序列的二维有限脉冲响应滤波器装置包括二维有限脉冲响应滤波器，其在多个连续时钟周期中的每一个期间操作，以在预定的通过将空间阵列中的一组数字字中的每一个乘以相应的一组加权系数中的相应加权系数，并且对所得到的乘积求和以产生输出滤波的数字字来对图像的区域进行乘积。滤波器包括存储加权系数数据的存储器，其存储限定轮廓的加权系数数据，当轮廓绕轴旋转时，产生对应于滤波器所需二维响应特性的加权系数值的三维表示，第一计算装置响应于每个数字字从表示中相应加权系数的位置的轴计算半径，由此可以根据阵列中的每个位置从商店导出对应于各个加权系数的值相应半径的值，以及第二计算装置，用于将每个数字字乘以相应的一组加权系数的相应加权系数，并且对所得到的乘积求和以得到所需的输出滤波数字字。

96. 发明授权

US4768205A Switched capacitor adaptive line equalizer 失效
标题翻译：开关电容自适应线路均衡器
公开(公告)号：US4768205A
公开(公告)日：1988-08-30
申请号：US834682
申请日：1986-02-28
申请人： Kenji Nakayama
发明人： Kenji Nakayama
IPC分类号： H03H19/00 , H03H17/02 , H04B3/04 , H04B3/14
CPC分类号： H04B3/04 , H03H17/0202
摘要： A switched capacitor adaptive line equalizer for use in digital communication system adapted to receive input signals at a plurality of signal rates and to supply equalized output signals. Input signals are sent through a switched capacitor equalizer which includes a low-pass filter in order to control the frequency band of the input signals and a variable gain action which selectively sets a prescribed .sqroot.f characteristic in response to the output of the low-pass filter. A control circuit responsive to the output of the switched capacitor equalizer and the input signal rate selectively adjusts to the characteristic of the switched capacitor equalizer means. Input signals are processed on a time division basis in two channels of the variable gain section, to select the operating characteristic on one of the channels while another operation is performed on the other channel.
摘要翻译：一种用于数字通信系统的开关电容器自适应线路均衡器，适于以多个信号速率接收输入信号并提供均衡的输出信号。输入信号通过包括低通滤波器的开关电容均衡器发送，以便控制输入信号的频带，以及可变增益动作，其响应于低通的输出而选择性地设置规定的2ROOT f特性过滤。响应于开关电容均衡器的输出和输入信号速率的控制电路选择性地根据开关电容器均衡器装置的特性进行调整。输入信号在可变增益部分的两个通道中以时分方式处理，以在另一个通道上执行另一操作时选择一个通道上的工作特性。

97. 发明授权

US3510581A Optimum postdetection filter for microwave radiometric mapping system 失效
标题翻译：用于微波辐射测绘系统的最佳POSTDETECTION滤波器
公开(公告)号：US3510581A
公开(公告)日：1970-05-05
申请号：US3510581D
申请日：1966-07-01
申请人： COLLINS RADIO CO
发明人： CRAIGLOW ROBERT L , HOLT JOHN M , ILIFF WALTER R
IPC分类号： G01S7/10 , G02B27/46 , G06E3/00 , H03H17/02 , H04N7/18 , H04N7/02
CPC分类号： G06E3/001 , G01S7/10 , G02B27/46 , H03H17/0202

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