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    • 94. 发明授权
    • Inkjet printed leadframe
    • 喷墨印刷引线框
    • US07824963B2
    • 2010-11-02
    • US12626440
    • 2009-11-25
    • Randall L. WalbergLuu T. NguyenAnindya Poddar
    • Randall L. WalbergLuu T. NguyenAnindya Poddar
    • H01L21/44H01L23/495
    • H01L21/4821H01L21/6835H01L23/49579H01L24/97H01L2221/68345H01L2924/14H01L2924/00
    • Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink. The nanoink is then cured to remove liquid content. The residual metallic leadframe or electrical interconnect pattern has a substantially consistent thickness of about 10 to 50 microns or less. An associated panel assembly includes a conductive substrate panel having multiple separate device arrays comprising numerous electrical interconnect patterns each, a plurality of integrated circuit devices mounted on the conductive substrate panel, and a molded cap that encapsulates the integrated circuit devices and associated electrical interconnect patterns. The molded cap is of substantially uniform thickness over each separate device array, and extends into the space between separate device arrays.
    • 公开了用于集成电路装置的用于喷墨印刷电互连图案的引线框架的装置和方法。 一种用于包装的装置包括适于高温处理的薄基板,以及使用金属纳米接头喷墨印刷到薄基板上的连接焊盘和接触区域。 然后将nanoink固化以除去液体内容物。 剩余的金属引线框架或电互连图案具有约10至50微米或更小的基本一致的厚度。 相关联的面板组件包括导电衬底面板,该导电衬底面板具有多个单独的器件阵列,每个单独的器件阵列包括多个电互连图案,每个均包括安装在导电衬底面板上的多个集成电路器件,以及封装集成电路器件和相关联的电互连图案的模制帽。 模制帽在每个分离的装置阵列上具有基本均匀的厚度,并且延伸到分离的装置阵列之间的空间中。
    • 95. 发明申请
    • Cu-ni-si system alloy
    • 铜镍系合金
    • US20100000637A1
    • 2010-01-07
    • US12311401
    • 2007-09-21
    • Takaaki Hatano
    • Takaaki Hatano
    • C22F1/08C22C9/06C22C9/04
    • H01L23/49579C21D1/25C22C9/06C22F1/00C22F1/08H01L2924/0002H01L2924/00
    • The present invention provides Cu—Ni—Si system alloys for electronic material that with the addition of other alloy elements minimized, simultaneously exhibits enhanced electric conductivity, strength, bendability and stress relaxation performance. There are provided Cu—Ni—Si system alloys comprising 1.2 to 3.5 mass % Ni, Si in a concentration (mass %) of ⅙ to ¼ of Ni concentration (mass %) and the balance Cu and impurities whose total amount is 0.05 mass % or less, the Cu—Ni—Si system alloys having its configuration of crystal grains and width of a precipitate-free zone regulated so as to fall within appropriate ranges by controlling solution treatment conditions, aging treatment conditions and degree of a reduction ratio. Thus, there can be provided copper alloys strip of 55 to 62% IACS electric conductivity and 550 to 700 MPa tensile strength, being free from cracking at 180° bending test of 0 radius and exhibiting a stress relaxation ratio, as measured on heating at 150° C. for 1000 hr, of 30% or less.
    • 本发明提供了一种用于电子材料的Cu-Ni-Si系合金,其中通过添加其它合金元素最小化,同时表现出增强的导电性,强度,弯曲性和应力松弛性能。 提供了Cu-Ni-Si系合金,其含有1.2〜3.5质量%的Ni,Si,其浓度(质量%)为Ni浓度的1/6〜¼(质量%),余量为Cu和总量为0.05的杂质 质量%以下,通过控制溶液处理条件,时效处理条件和缩小比例,将其晶粒结构和无沉淀区域宽度的Cu-Ni-Si系合金调节为适当范围 。 因此,可以提供55〜62%IACS电导率和550〜700MPa拉伸强度的铜合金条,在180°弯曲试验下不发生0°半径的破裂,并显示应力松弛率,如在150℃加热 ℃,1000小时,30%以下。