专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20120221922A1 MEMORY MANAGEMENT SYSTEM AND METHOD 有权
标题翻译：内存管理系统与方法
公开(公告)号：US20120221922A1
公开(公告)日：2012-08-30
申请号：US13442284
申请日：2012-04-09
申请人： Jon C. R. Bennett
发明人： Jon C. R. Bennett
IPC分类号： H03M13/00
CPC分类号： G06F3/065 , G06F3/0608 , G06F3/0616 , G06F3/0619 , G06F3/064 , G06F3/0652 , G06F3/0653 , G06F3/0688 , G06F3/0689 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F11/1076 , G06F11/108 , G06F12/0246 , G06F12/0866 , G11B20/1833 , G11B2220/60 , G11C16/10 , G11C16/16 , G11C16/26 , G11C29/28 , G11C29/52
摘要： A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.
摘要翻译：描述了一种存储系统及其操作方法，其中存储器系统用于以RAIDed方式存储数据。可以检索存储的数据，包括奇偶校验数据，使得当已经接收到没有奇偶校验数据的所存储的数据中的第一个或来自除了一个存储器模块和奇偶校验数据的所有存储的数据之前，存储的数据被恢复。管理低写入数据加载的数据写入，使得在一段时间间隔内只有一个RAID条带的存储器模块被写入或擦除。

92. 发明申请

US20120072788A1 INTEGRATED CIRCUIT WITH MEMORY BUILT-IN SELF TEST (MBIST) CIRCUITRY HAVING ENHANCED FEATURES AND METHODS 有权
标题翻译：集成电路与存储器内置自检（MBIST）具有增强特性和方法的电路
公开(公告)号：US20120072788A1
公开(公告)日：2012-03-22
申请号：US12883441
申请日：2010-09-16
申请人： Wei-Yu Chen , Kevin Badgett , Kay Hesse
发明人： Wei-Yu Chen , Kevin Badgett , Kay Hesse
IPC分类号： G11C29/36 , G06F11/27
CPC分类号： G11C29/36 , G11C29/06 , G11C29/28 , G11C2029/2602
摘要： Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.
摘要翻译：具有存储器内置自检（MBIST）电路和方法的集成电路被公开，其采用增强的特征。在本发明的一个方面，提供了一种集成电路，其具有MBIST电路，其被配置为串行测试集成电路的部件内的多个存储元件阵列，并且还对串行测试阵列进行并行初始化。在本发明的另一方面，使用MBIST电路将阵列的存储元件设置为第一状态，然后在老化操作期间将其置于反向状态，以将两个相对状态中的每一个保持期望的时间，以便要么强制集成电路部件的故障或者产生超过初级阶段的预应力部件。

93. 发明申请

US20110063909A1 NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD OF TESTING THE SAME 审中-公开
标题翻译：非易失性半导体存储器及其测试方法
公开(公告)号：US20110063909A1
公开(公告)日：2011-03-17
申请号：US12713674
申请日：2010-02-26
申请人： Yukio KOMATSU
发明人： Yukio KOMATSU
IPC分类号： G11C16/06 , G11C16/04 , G11C29/00
CPC分类号： G11C29/28 , G11C16/04 , G11C29/50012
摘要： A memory cell array and a peripheral circuit are provided. The memory cell array has a plurality of blocks which are erasing units respectively. Each of the blocks includes a plurality of memory cells. A block control unit operates according to input signals from outside and controls operation of the blocks. A ready/busy control circuit outputs a busy signal during a period of operation implementation for a block selected from the blocks, in response to an output from the block control unit. The ready/busy control circuit outputs a ready signal out of the period of the operation implementation for the selected block. A registration control unit registers the selected block as a bad block, in the case that the ready/busy control circuit outputs a busy signal when the registration control unit receives a bad block identification command.
摘要翻译：提供存储单元阵列和外围电路。存储单元阵列具有分别是擦除单元的多个块。每个块包括多个存储单元。块控制单元根据来自外部的输入信号进行操作并控制块的操作。响应于来自块控制单元的输出，就绪/忙控制电路在从块中选择的块的操作实施期间输出忙信号。准备/繁忙控制电路在所选块的操作实施期间输出就绪信号。在登录控制单元接收到不良块识别命令时，就绪/忙控制电路输出忙信号的情况下，登记控制单元将所选择的块登记为坏块。

94. 发明授权

US07904767B2 Semiconductor memory testing device and method of testing semiconductor using the same 失效
公开(公告)号：US07904767B2
公开(公告)日：2011-03-08
申请号：US12205036
申请日：2008-09-05
申请人： Byoung Kwon Park
发明人： Byoung Kwon Park
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C29/28 , G11C2029/1202 , G11C2029/2602
摘要： The semiconductor memory testing device includes a test signal decoder decoding burn-in test mode signals which generates a first test signal for use in controlling entire main wordlines and which generates a second test signal for use in controlling sub wordlines. When the first and second test signals are in an disabled state, the semiconductor memory testing device also includes a plurality of bank control units generating a multi wordline test mode signal as a multi wordline test signal corresponding to a bank control signal, and simultaneously enabling a plurality of wordlines in accordance to the multi wordline test signal to perform a test. The semiconductor memory testing device reduces a testing time and current consumption and thus enhances a more stable voltage drop when performing continuous multi wordline test on a per bank basis.

95. 发明申请

US20090175105A1 Semiconductor memory device that includes an address coding method for a multi-word line test 失效
标题翻译：半导体存储器件，其包括用于多字线测试的地址编码方法
公开(公告)号：US20090175105A1
公开(公告)日：2009-07-09
申请号：US12318685
申请日：2009-01-06
申请人： Hyun-ki Kim , Whee-Jin Kwon
发明人： Hyun-ki Kim , Whee-Jin Kwon
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C29/28 , G11C2029/1202 , G11C2029/1802
摘要： Example embodiments relate to a semiconductor memory device that includes an address coding method for a multi-word line test, for example, an address coding method to test a semiconductor memory device having a cell block row selection circuit. The semiconductor memory device may include a plurality of memory cell blocks, where each memory cell block may include memory cells coupled to a bit line. The method may include coding row addresses of the memory cell block by dividing one or more row addresses corresponding to cell blocks of the memory cell block to create sub-cell blocks and adding the sub-cell blocs into the main cell blocks to create a logical memory block, which enables word lines of the main cell blocks and sub-cell blocks at the same time.
摘要翻译：示例性实施例涉及一种半导体存储器件，其包括用于多字线测试的地址编码方法，例如，用于测试具有单元块行选择电路的半导体存储器件的地址编码方法。半导体存储器件可以包括多个存储器单元块，其中每个存储器单元块可以包括耦合到位线的存储器单元。该方法可以包括通过划分与存储器单元块的单元块相对应的一个或多个行地址来编码存储器单元块的行地址以创建子单元块并将子单元块添加到主单元块中以创建逻辑存储块，其同时启用主单元块和子单元块的字线。

96. 发明申请

US20080250270A1 Memory management system and method 有权
标题翻译：内存管理系统和方法
公开(公告)号：US20080250270A1
公开(公告)日：2008-10-09
申请号：US12079364
申请日：2008-03-26
申请人： Jon C. R. Bennett
发明人： Jon C. R. Bennett
IPC分类号： G06F11/20 , G06F12/00 , G06F12/02
CPC分类号： G06F3/065 , G06F3/0608 , G06F3/0616 , G06F3/0619 , G06F3/064 , G06F3/0652 , G06F3/0653 , G06F3/0688 , G06F3/0689 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F11/1076 , G06F11/108 , G06F12/0246 , G06F12/0866 , G11B20/1833 , G11B2220/60 , G11C16/10 , G11C16/16 , G11C16/26 , G11C29/28 , G11C29/52
摘要： A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.
摘要翻译：描述了一种存储系统及其操作方法，其中存储器系统用于以RAIDed方式存储数据。可以检索存储的数据，包括奇偶校验数据，使得当已经接收到没有奇偶校验数据的所存储的数据中的第一个或来自除了一个存储器模块和奇偶校验数据的所有存储的数据之前，存储的数据被恢复。管理低写入数据加载的数据写入，使得在一段时间间隔内只有一个RAID条带的存储器模块被写入或擦除。

97. 发明申请

US20060126382A1 Method for reading non-volatile memory cells 有权
标题翻译：读取非易失性存储单元的方法
公开(公告)号：US20060126382A1
公开(公告)日：2006-06-15
申请号：US11007332
申请日：2004-12-09
申请人： Eduardo Maayan , Guy Cohen , Boaz Eitan
发明人： Eduardo Maayan , Guy Cohen , Boaz Eitan
IPC分类号： G11C16/06
CPC分类号： G11C29/28 , G11C16/04 , G11C16/0475 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/50 , G11C29/50004
摘要： A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level for correct reading of at least one history cell, selecting a memory read reference level according to the first read reference level, and reading non-volatile memory array cells associated with the at least one history cell using the memory read reference level.
摘要翻译：一种方法包括根据不同组存储器单元的阈值电压分布的变化来改变用于读取一组存储器单元的读取参考电平。改变步骤包括确定用于正确读取至少一个历史单元的历史读取参考电平，根据第一读取参考电平选择存储器读取参考电平，以及读取与至少一个历史单元相关联的非易失性存储器阵列单元使用内存读取参考级别。

98. 发明授权

US06977855B2 Apparatus and method for dynamically repairing a semiconductor memory 有权
标题翻译：用于动态修复半导体存储器的装置和方法
公开(公告)号：US06977855B2
公开(公告)日：2005-12-20
申请号：US11006045
申请日：2004-12-07
申请人： Brian P. Callaway , Aaron M. Baum
发明人： Brian P. Callaway , Aaron M. Baum
IPC分类号： G11C29/00 , G11C29/28 , G11C16/04
CPC分类号： G11C29/72 , G11C29/006 , G11C29/26 , G11C29/28 , G11C29/38 , G11C29/44 , G11C29/4401 , G11C29/76 , G11C29/785 , G11C2029/2602 , G11C2029/3602 , G11C2029/4002
摘要： An architecture for dynamically repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes circuitry for dynamically storing memory element remapping information. Memory is tested for errors by writing, then reading a plurality of memory blocks, such as rows or columns, in parallel. Memory is dynamically reprogrammed in order to remap unused spare memory elements for failed memory elements when errors are detected. Unused spare memory elements are remapped utilizing a circuit that overrides unblown fuses or antifuses.
摘要翻译：用于动态修复诸如动态随机存取存储器（DRAM）的半导体存储器的架构包括用于动态存储存储元件重映射信息的电路。通过写入来测试存储器的错误，然后并行地读取多个存储器块，例如行或列。当检测到错误时，内存被动态重新编程，以便重新映射用于故障存储器元件的未使用的备用存储器元件。未使用的备用存储器元件使用覆盖未熔丝熔丝或反熔丝的电路进行重新映射。

99. 发明申请

US20050188286A1 METHOD FOR DETERMINING INTEGRITY OF MEMORY 有权
标题翻译：用于确定存储器的完整性的方法
公开(公告)号：US20050188286A1
公开(公告)日：2005-08-25
申请号：US10708276
申请日：2004-02-20
申请人： Po-Wei Liu , Chang-Lien Wu
发明人： Po-Wei Liu , Chang-Lien Wu
IPC分类号： G11C29/00 , G11C29/28
CPC分类号： G11C29/28
摘要： A method for testing the integrity of a memory with defective sections under a plurality of operating environments includes testing the memory with defective sections under a plurality of operating environments, recording results of each operating environment test, and comparing the results of the tests. If the results of are the same, the memory with defective sections is declared to have integrity. If not, the memory with defective sections is declared to not have integrity.
摘要翻译：一种用于在多个操作环境下测试具有缺陷部分的存储器的完整性的方法包括在多个操作环境下测试具有缺陷部分的存储器，记录每个操作环境测试的结果，以及比较测试结果。如果结果相同，则声明具有缺陷部分的内存具有完整性。如果没有，具有缺陷部分的内存被声明为不完整。

100. 发明申请

US20050083739A1 Apparatus and method for dynamically repairing a semiconductor memory 有权
公开(公告)号：US20050083739A1
公开(公告)日：2005-04-21
申请号：US11006045
申请日：2004-12-07
申请人： Brian Callaway , Aaron Baum
发明人： Brian Callaway , Aaron Baum
IPC分类号： G11C29/00 , G11C29/28 , G11C5/00
CPC分类号： G11C29/72 , G11C29/006 , G11C29/26 , G11C29/28 , G11C29/38 , G11C29/44 , G11C29/4401 , G11C29/76 , G11C29/785 , G11C2029/2602 , G11C2029/3602 , G11C2029/4002
摘要： An architecture for dynamically repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes circuitry for dynamically storing memory element remapping information. Memory is tested for errors by writing, then reading a plurality of memory blocks, such as rows or columns, in parallel. Memory is dynamically reprogrammed in order to remap unused spare memory elements for failed memory elements when errors are detected. Unused spare memory elements are remapped utilizing a circuit that overrides unblown fuses or antifuses.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式