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91. 发明申请

US20160313978A1 CIRCUITRY AND METHODS FOR IMPLEMENTING GALOIS-FIELD REDUCTION 有权
标题翻译：用于实现GALOIS场减少的电路和方法
公开(公告)号：US20160313978A1
公开(公告)日：2016-10-27
申请号：US14694396
申请日：2015-04-23
申请人： Altera Corporation
发明人： Pohrong Rita Chu
IPC分类号： G06F7/72
CPC分类号： G06F7/724
摘要： Galois-field reduction circuitry for reducing a Galois-field expansion value, using an irreducible polynomial, includes a plurality of memories, each for storing a respective value derived from the irreducible polynomial and a respective combination of expansion bit values, wherein expansion bits of the expansion value address the plurality of memories to output one or more of the respective values. The Galois-field reduction circuitry also includes exclusive-OR circuitry for combining output of the plurality of memories with in-field bits of said expansion value. There are also a method of operating such Galois-field reduction circuitry to reduce a Galois-field expansion value, a programmable integrated circuit device incorporating the circuitry, a method of performing a Galois-field multiplication operation on such a programmable integrated circuit device, and a method of configuring a programmable integrated circuit device to perform such a Galois-field multiplication operation.
摘要翻译：使用不可约多项式来降低伽罗瓦域扩展值的伽罗瓦域减少电路包括多个存储器，每个存储器用于存储从不可约多项式导出的相应值和扩展位值的相应组合，其中扩展位扩展值寻址多个存储器以输出相应值中的一个或多个。伽罗瓦域还原电路还包括用于将多个存储器的输出与所述扩展值的现场比特组合的异或电路。还有一种操作这种伽罗瓦域减少电路以减少伽罗瓦域扩展值的方法，结合电路的可编程集成电路装置，在这种可编程集成电路装置上执行伽罗瓦域乘法运算的方法，以及一种配置可编程集成电路器件以执行这样的伽罗瓦域乘法运算的方法。

92. 发明授权

US09417847B2 Low depth combinational finite field multiplier 有权
标题翻译：低深度组合有限域乘法器
公开(公告)号：US09417847B2
公开(公告)日：2016-08-16
申请号：US13231129
申请日：2011-09-13
申请人： Sergey B. Gashkov , Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav D. Ivanovic , Anatoly A. Chasovshikh , Alexei V. Galatenko , Igor V. Kucherenko
发明人： Sergey B. Gashkov , Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav D. Ivanovic , Anatoly A. Chasovshikh , Alexei V. Galatenko , Igor V. Kucherenko
IPC分类号： G06F7/72 , G06F17/50
CPC分类号： G06F7/724 , G06F17/505
摘要： A method for generating a design of a multiplier is disclosed. The method generally includes steps (A) to (C). Step (A) may generate a first circuit comprising a plurality of polynomial results of a particular multiplier scheme based on a plurality of parameters of the multiplier. The first circuit is generally configured to multiply a plurality of polynomials. Step (B) may generate a second circuit comprising a plurality of polynomial evaluators based on the parameters. The second circuit may be (i) connected to the first circuit and (ii) configured to evaluate a polynomial modulo operation. Step (C) may generate the design of the multiplier in combinational logic by optimizing a depth of a plurality of logic gates through the first circuit and the second circuit. A product of the polynomials generally resides in a finite field.
摘要翻译：公开了一种生成乘法器设计的方法。该方法通常包括步骤（A）至（C）。步骤（A）可以基于乘法器的多个参数来生成包括特定乘法器方案的多个多项式结果的第一电路。第一电路通常被配置为乘以多个多项式。步骤（B）可以基于参数生成包括多个多项式评估器的第二电路。第二电路可以是（i）连接到第一电路，（ii）被配置为评估多项式模运算。步骤（C）可以通过优化通过第一电路和第二电路的多个逻辑门的深度来生成组合逻辑中乘法器的设计。多项式的乘积通常位于有限域中。

93. 发明申请

US20160210867A1 NAVIGATION AID METHOD BASED ON METEOROLOGICAL CONDITIONS 有权
标题翻译：基于气象条件的导航辅助方法
公开(公告)号：US20160210867A1
公开(公告)日：2016-07-21
申请号：US14992929
申请日：2016-01-11
申请人： THALES
发明人： Christophe PIERRE , Rémy AULETTO , Benoît DACRE-WRIGHT
IPC分类号： G08G5/00 , G01W1/02 , G06F7/72 , G01C21/20
CPC分类号： G08G5/0039 , G01C21/20 , G01W1/02 , G06F7/724 , G08G5/0034 , G08G5/0052 , G08G5/0091
摘要： A navigation aid method for an aircraft flying a reference trajectory between a point of departure and a point of arrival subject to a field of wind vectors comprises: decomposing the reference trajectory into a plurality of discrete waypoints Pi, loading meteorological data comprising the field of wind vectors, iterating the following steps N times, to generate an improved trajectory: for each waypoint Pi named current point, determining a reference plane, determining an orthonormal reference frame, determining a wind curl ((∇W)Pi), determining a sign of the projection of the wind curl on axis zi ((∇W)zi Pi), determining a direction of displacement from the current point Pi to a new current waypoint Pi′, determining a line of displacement, determining a displacement distance, determining the new current waypoint, determining a new trajectory, assigning the new waypoints Pi′ determined in the preceding iteration to the waypoints Pi for the next iteration.
摘要翻译：一种用于飞行在出发点与受到风向量场的到达点之间的参考轨迹的飞行器的导航辅助方法包括：将参考轨迹分解为多个离散航路点Pi，加载包括风场的气象数据向量，迭代以下步骤N次，以产生改进的轨迹：对于每个路点Pi命名当前点，确定参考平面，确定正交参考帧，确定风卷曲（（∇W）Pi），确定确定从当前点Pi到新的当前路点Pi'的位移方向，确定位移线，确定位移距离，确定新的当前点Pi 确定一个新的轨迹，将上一次迭代中确定的新路点Pi'分配给下一次迭代的路点Pi。

94. 发明申请

US20160147504A1 CUBIC ROOT OF A GALOIS FIELD ELEMENT 有权
标题翻译： GALOIS场元素的CUBIC根
公开(公告)号：US20160147504A1
公开(公告)日：2016-05-26
申请号：US14551110
申请日：2014-11-24
申请人： APPLE INC.
发明人： Micha Anholt , Moti Teitel
IPC分类号： G06F7/552 , G06F7/72
CPC分类号： G06F7/724 , G06F7/552 , G06F7/5525 , G06F2207/5526
摘要： A method includes receiving a first element of a Galois Field of order qm, where q is a prime number and m is a positive integer. The first element is raised to a predetermined power so as to form a second element z, wherein the predetermined power is a function of qm and an integer p, where p is a prime number which divides qm−1. The second element z is raised to a pth power to form a third element. If the third element equals the first element, the second element multiplied by a pth root of unity raised to a respective power selected from a set of integers between 0 and p−1 is output as at least one root of the first element.
摘要翻译：一种方法包括接收秩序q m的伽罗瓦域的第一元素，其中q是素数，m是正整数。将第一元件升高到预定的功率以形成第二元件z，其中预定功率是qm和整数p的函数，其中p是除以qm-1的素数。第二元件z升高到第p个功率以形成第三元件。如果第三元素等于第一元素，则将第二元素乘以第p个单位根提升到从0和p-1之间的整数集合中选择的相应功率作为第一元素的至少一个根。

95. 发明授权

US09311052B2 Method of performing multiplication operation in binary extension finite field 有权
标题翻译：在二进制扩展有限域中执行乘法运算的方法
公开(公告)号：US09311052B2
公开(公告)日：2016-04-12
申请号：US14084767
申请日：2013-11-20
申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
发明人： Dongsoo Kim , Junyoung Son , Sangwoon Yang
IPC分类号： G06F7/00 , G06F7/72 , G06F7/523
CPC分类号： G06F7/724 , G06F7/523
摘要： In a method of performing a multiplication operation in a binary extension finite field, a polynomial defined by ∑ n = 0 W - 1 ⁢ C n · z n is produced by expanding polynomial basis multiplication for multiplication of two polynomials a(z) and b(z) in a binary extension finite field. A mapping table is generated in which bit values having pieces of information about respective terms of the produced polynomial are mapped to respective rows. A code for calculating the polynomial, produced by expanding the polynomial basis multiplication for the multiplication of the two polynomials, with reference to the mapping table is generated. A multiplication operation of the two polynomials a(z) and b(z) in the binary extension finite field is performed by executing the code for calculating the polynomial wherein a ⁡ ( z ) = ∑ n = 0 m - 1 ⁢ a n · z n , b ⁡ ( z ) = ∑ n = 0 m - 1 ⁢ b n · z n , and W denotes a number of bits of a word that is an operation processing unit of a processor.
摘要翻译：在二进制扩展有限域中进行乘法运算的方法中，通过扩展多项式乘法求出由Σn = 0 W -1 C n·z n定义的多项式，用于乘以两个多项式a（z）和b（ z）在二进制扩展有限域中。产生映射表，其中具有关于所生成的多项式的各个项的信息的位的值被映射到相应的行。生成用于计算通过扩展用于两个多项式的乘法的多项式基乘法参考映射表而产生的多项式的代码。通过执行用于计算多项式的代码来执行二进制扩展有限域中的两个多项式a（z）和b（z）的乘法运算，其中a（z）=Σn= 0 m-1·an·zn ，b⁡（z）=Σn= 0m-1bn·zn，W表示作为处理器的操作处理单元的字的位数。

96. 发明授权

US09235554B2 Method and system of improved Galois multiplication 有权
标题翻译：改进Galois乘法的方法和系统
公开(公告)号：US09235554B2
公开(公告)日：2016-01-12
申请号：US13842542
申请日：2013-03-15
申请人： Walter J. Downey
发明人： Walter J. Downey
IPC分类号： G06F7/00 , G06F17/10 , G06F7/72
CPC分类号： G06F7/724 , G06F17/10 , G06F2207/72 , H03M13/1515
摘要： Embodiments of the invention include an apparatus for performing Galois multiplication using an enhanced Galois table. Galois multiplication may include converting a first and second multiplicand to exponential forms using a Galois table, adding the exponential forms of the first and second multiplicands, and converting the added exponential forms of the first and second multiplicands to a decimal equivalent binary form using the Galois table to decimal equivalent binary result of the Galois multiplication.
摘要翻译：本发明的实施例包括一种使用增强伽罗瓦表执行伽罗瓦乘法的装置。伽罗瓦乘法可以包括使用伽罗瓦表将第一和第二被乘数转换成指数形式，加上第一和第二被乘数的指数形式，并且使用伽罗瓦将第一和第二被乘数的相加指数形式转换为十进制等价二进制形式表格为十进制等值二进制结果的Galois乘法。

97. 发明授权

US09183076B2 Using carry-less multiplication (CLMUL) to implement erasure code 有权
标题翻译：使用无进位乘法（CLMUL）来实现擦除代码
公开(公告)号：US09183076B2
公开(公告)日：2015-11-10
申请号：US13866453
申请日：2013-04-19
申请人： FutureWei Technologies, Inc.
发明人： James Hughes
IPC分类号： G06F11/08 , G06F11/10 , G06F7/72 , G06F7/00 , G06F7/53 , G06F9/30
CPC分类号： G06F11/08 , G06F7/00 , G06F7/53 , G06F7/724 , G06F9/3001 , G06F11/1076 , G06F2211/1028 , H03M13/134 , H03M13/373 , H03M13/3761
摘要： Systems and methods for using carry-less multiplication (CLMUL) to implement erasure code are provided. An embodiment method of using CLMUL to implement erasure code includes initiating, with a processor, a first CLMUL call to calculate a first product of a data bit word and a constant, partitioning, with the processor, the first product into a high portion and a low portion, and initiating, with the processor, a second CLMUL call to calculate a second product of the high portion and a hexadecimal number portion, a bit size of the second product less than a bit size of the first product. The second product, or a third product generated by a third CLMUL call, is used to calculate a parity bit. Because the second product or the third product has a number of bits equivalent to the number of bits used by the processor, the erasure codes are more efficiently implemented.
摘要翻译：提供了使用无进位乘法（CLMUL）来实现擦除代码的系统和方法。使用CLMUL来实现擦除代码的实施方式包括：用处理器启动第一CLMUL调用以计算数据比特字和常数的第一乘积，将处理器与第一产品分隔成高部分和并且与所述处理器一起发起第二CLMUL调用以计算所述高部分和十六进制数部分的第二乘积，所述第二乘积的位大小小于所述第一乘积的位大小。第二个产品或由第三个CLMUL调用生成的第三个产品用于计算奇偶校验位。因为第二产品或第三产品具有与处理器使用的位数相当的位数，所以更有效地实现擦除代码。

98. 发明授权

US09146708B2 Implementation of arbitrary galois field arithmetic on a programmable processor 有权
标题翻译：在可编程处理器上实现任意伽罗瓦域算术
公开(公告)号：US09146708B2
公开(公告)日：2015-09-29
申请号：US12991877
申请日：2009-05-07
申请人： Mayan Moudgill
发明人： Mayan Moudgill
IPC分类号： G06F7/72 , G06F9/30
CPC分类号： G06F7/724 , G06F7/722 , G06F9/3001
摘要： A method for a Galois Field multiply includes executing first and second instructions. The first instruction includes receiving a first input, such as a first variable, receiving a second input, such as a second variable, performing a polynomial multiplication over GF(2m), using the first and second inputs, and producing a product. The second instruction includes receiving a third input, which may be the product from the first instruction, receiving a fourth input, which is a predetermined generator polynomial to operate upon the product, receiving a fifth input, which is a length of the predetermined generator polynomial, to limit operation of the predetermined generator polynomial upon the product, and computing, via the predetermined generator polynomial limited by the length, a modulus of the product with respect to a divisor. A hardware block is also described.
摘要翻译： Galois域乘法的方法包括执行第一和第二指令。第一指令包括使用第一和第二输入接收诸如第一变量的第一输入，接收诸如第二变量的第二输入，使用GF（2m）执行多项式乘法，并产生乘积。第二指令包括接收第三输入，其可以是来自第一指令的乘积，接收作为对产品进行操作的预定生成多项式的第四输入，接收作为预定生成多项式的长度的第五输入，以限制产品上的预定生成多项式的运算，并且经由长度限制的预定生成多项式计算乘积相对于除数的模数。还描述了硬件块。

99. 发明申请

US20150261504A1 VECTORIZED GALOIS FIELD MULTIPLICATION 有权
标题翻译： VECTORIZED GALOIS场多项式
公开(公告)号：US20150261504A1
公开(公告)日：2015-09-17
申请号：US14291942
申请日：2014-05-30
申请人： International Business Machines Corporation
发明人： James R. Cuffney , John G. Rell, JR. , Eric M. Schwarz , Patrick M. West, JR.
IPC分类号： G06F7/72
CPC分类号： G06F7/724 , G06F2207/72
摘要： Embodiments relate to vectorized Galois field multiplication. An aspect includes an input of first and second input operands of equal sizes into a single hardware tree, a calculation of a predicted parity as a parity of the first input operand ANDed with a parity of the second input operand, a comparison of the predicted parity with a parity generated on a final result of a Galois field multiplication of the first and second operands and a raising of an error based on a mismatch between the predicted parity and the generated parity.
摘要翻译：实施例涉及矢量化伽罗瓦域乘法。一方面包括将具有相同大小的第一和第二输入操作数输入到单个硬件树中，将预测奇偶校验作为第一输入操作数的奇偶校验与第二输入操作数的奇偶校验进行运算，预测奇偶校验的比较具有在第一和第二操作数的伽罗瓦域乘法的最终结果上产生的奇偶校验，以及基于预测奇偶校验和产生的奇偶校验之间的不匹配引起的误差的增加。

100. 发明授权

US08744072B2 Exponentiation method resistant against side-channel and safe-error attacks 有权
标题翻译：指数方法抵御侧向通道和安全错误攻击
公开(公告)号：US08744072B2
公开(公告)日：2014-06-03
申请号：US13138584
申请日：2010-03-01
申请人： Marc Joye
发明人： Marc Joye
IPC分类号： H04K1/00 , H04L9/00 , H04L9/28 , H04L9/30 , G06F7/72 , G06F7/38
CPC分类号： H04L9/002 , G06F7/38 , G06F7/72 , G06F7/723 , G06F7/724 , G06F7/728 , G06F2207/7261 , H04L9/003 , H04L9/004 , H04L9/30 , H04L9/3066
摘要： An exponentiation method resistant against side-channel attacks and safe-error attacks. Input to the method is g in a multiplicatively written group G and a /-digit exponent d with a radix m>1 and output is z=gd-1·(d−1) is expressed as a series of (/−1) non-zero digits, d*0 . . . d*I-2, in the set {m−1, . . . , 2m−2} and an extra digit d*I-1 that is equal to dI-1−1, where dI-1 represents the most significant radix-m digit of d, and gd-1 is evaluated through a m-ary exponentiation algorithm on input g and (d−1) represented by d*0 . . . d*I-1. Also provided are an apparatus and a computer program product.
摘要翻译：一种抗侧向攻击和安全错误攻击的取幂方法。该方法的输入为g，乘法编写的组G和a / -digit指数d，基数m> 1，输出为z = gd-1·（d-1）表示为一系列（/ -1）非零数字，d * 0。。。 d * I-2，在集合{m-1，。。。，2m-2}和等于dI-1-1的额外数字d * I-1，其中dI-1表示d的最显着的rad-m数字，并且gd-1通过m-ar 由d * 0表示的输入g和（d-1）的求幂算法。。。 d * I-1。还提供了一种装置和计算机程序产品。

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