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91. 发明授权

US4805198A Clock multiplier/jitter attenuator 失效
标题翻译：时钟乘法器/抖动衰减器
公开(公告)号：US4805198A
公开(公告)日：1989-02-14
申请号：US51985
申请日：1987-05-19
申请人： Kenneth J. Stern , Navdeep S. Sooch , Jerrell P. Hein
发明人： Kenneth J. Stern , Navdeep S. Sooch , Jerrell P. Hein
IPC分类号： G06F5/10 , H03L7/085 , H03L7/099 , H03L7/181 , H04J3/06 , H04L7/00
CPC分类号： G06F5/10 , H03L7/085 , H03L7/0991 , H03L7/181 , H04J3/0626 , G06F2205/061
摘要： A clock multiplier/jitter attenuator circuit provides a stable clock which is a multiple frequency of the average frequency of an external digital data stream. The external data is written into successive storage cells of a FIFO at its own clock rate and read out of the FIFO at the rate of an internal clock signal which is formed by frequency dividing the stable clock. The relative locations of the cell being written into and the cell being read out of are determined at periodic time intervals, and these relative locations are used to adjust the frequency of an internal oscillator which generates the stable clock. The instantaneous jitter on the digital data stream is absorbed by the FIFO.
摘要翻译：时钟倍增器/抖动衰减器电路提供稳定的时钟，其是外部数字数据流的平均频率的多个频率。外部数据以其自己的时钟速率写入FIFO的连续存储单元，并以由分频稳定时钟形成的内部时钟信号的速率读出FIFO。以周期性的时间间隔确定要写入的单元和读出的单元的相对位置，并且这些相对位置用于调整产生稳定时钟的内部振荡器的频率。数字数据流上的瞬时抖动被FIFO吸收。

92. 发明授权

US4344132B1 失效
公开(公告)号：US4344132B1
公开(公告)日：1984-03-27
申请号：US10378279
申请日：1979-12-14
IPC分类号： G06F3/06 , G06F3/00 , G06F5/06
CPC分类号： G06F5/06 , G06F3/007 , G06F2205/061

93. 发明授权

US11967960B2 Methods and apparatus for synchronizing data transfers across clock domains using heads-up indications 有权
公开(公告)号：US11967960B2
公开(公告)日：2024-04-23
申请号：US17389749
申请日：2021-07-30
申请人： Advanced Micro Devices, Inc.
发明人： David M. Dahle , Richard Martin Born , Deepesh John
IPC分类号： H03L7/081 , G06F5/08 , H03L7/087 , H03L7/195
CPC分类号： H03L7/0814 , G06F5/08 , H03L7/087 , H03L7/195 , G06F2205/061
摘要： Methods and apparatus for synchronizing data transfers across clock domains for using heads-up indications. An integrated circuit includes a first-in first-out buffer (FIFO); a memory controller configured to operate in a first clock domain and coupled to the FIFO, the first clock domain associated with a first clock signal; a data fabric configured to operate in a second clock domain and coupled to the FIFO, the second clock domain associated with a second clock signal, a second frequency of the second clock signal being different from a first frequency of the first clock signal; and a controller coupled to the FIFO. In some instances, the controller determines a phase relationship between the first clock signal and the second clock signal; monitors one or more first clock edges of the first clock signal and one or more second clock edges of the second clock signal; and sends a first heads-up signal to the memory controller.

94. 发明授权

US09330740B1 First-in first-out circuits and methods 有权
标题翻译：先进先出的电路和方法
公开(公告)号：US09330740B1
公开(公告)日：2016-05-03
申请号：US14133245
申请日：2013-12-18
申请人： Altera Corporation
发明人： Gregg William Baeckler , David W. Mendel
IPC分类号： G11C7/22
CPC分类号： G11C7/222 , G06F5/14 , G06F2205/061 , G11C19/287
摘要： A first first-in first-out (FIFO) circuit includes a storage circuit, a second first-in first-out (FIFO) circuit, and a third first-in first-out (FIFO) circuit. The storage circuit stores write data at a write address in response to a write clock signal. The storage circuit outputs read data from a read address in response to a read clock signal. A write pointer indicating the write address is synchronized with the write clock signal. A read pointer indicating the read address is synchronized with the read clock signal. The second first-in first-out (FIFO) circuit synchronizes the write pointer with the read clock signal. The third first-in first-out (FIFO) circuit synchronizes the read pointer with the write clock signal.
摘要翻译：第一先进先出（FIFO）电路包括存储电路，第一先进先出（FIFO）电路和第三先进先出（FIFO）电路。存储电路响应于写入时钟信号将写入数据存储在写入地址处。存储电路响应于读时钟信号从读地址输出读数据。指示写地址的写指针与写时钟信号同步。指示读地址的读指针与读时钟信号同步。第二先进先出（FIFO）电路使写指针与读时钟信号同步。第一先进先出（FIFO）电路使读指针与写时钟信号同步。

95. 发明申请

US20150109531A1 CLOCK TRANSFER CIRCUIT, VIDEO PROCESSING SYSTEM, AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：时钟传输电路，视频处理系统和半导体集成电路
公开(公告)号：US20150109531A1
公开(公告)日：2015-04-23
申请号：US14553541
申请日：2014-11-25
申请人： Panasonic Intellectual Property Management Co., Ltd.
发明人： Yuuki NISHIO
IPC分类号： H04N5/08
CPC分类号： H04N5/08 , G06F5/06 , G06F2205/061 , G09G5/005 , G09G5/006 , G09G2340/0435 , G09G2370/10 , H04N7/0105 , H04N21/4305 , H04N21/43632
摘要： A clock transfer circuit receives input data synchronized with a first clock, and outputs, as output data, data synchronized with a second clock having a frequency different from that of the first clock. A write address controller is operating according to the first clock, and provides a write address to a memory. A read address controller is operating according to the second clock, and provides a read address to the memory. A cycle comparator compares the cycle of a predetermined event between the input data and the output data. Based on such a comparison result, the clock adjuster adjusts the frequency of the second clock.
摘要翻译：时钟传送电路接收与第一时钟同步的输入数据，并且输出与具有与第一时钟不同的频率的第二时钟同步的数据作为输出数据。写地址控制器根据第一时钟进行操作，并向存储器提供写地址。读地址控制器根据第二时钟进行操作，并向存储器提供读地址。循环比较器比较输入数据和输出数据之间的预定事件的周期。基于这样的比较结果，时钟调整器调节第二时钟的频率。

96. 发明申请

US20140310549A1 FIFO Clock and Power Management 审中-公开
标题翻译： FIFO时钟和电源管理
公开(公告)号：US20140310549A1
公开(公告)日：2014-10-16
申请号：US13861071
申请日：2013-04-11
申请人： APPLE INC.
发明人： Gilbert H. Herbeck
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3243 , G06F5/12 , G06F2205/061 , G06F2205/126 , Y02D10/126 , Y02D10/152
摘要： An apparatus and method for saving power when transmitting data across a clock boundary is disclosed. In one embodiment, an apparatus includes a FIFO coupled to receive data from circuitry in a first clock domain and output data to circuitry in a second clock domain. A first control circuit is responsible for writing data into the FIFO. A second control circuit is responsible for reading data from the FIFO. If the amount of data in the FIFO exceeds a first threshold, a power management circuit may place the first control circuit in a low power state. The second control circuit may monitor the amount of data in the FIFO. If the amount of data in the FIFO falls below a second threshold, it may assert an indication to the power management circuit. Thereafter, the power management circuit may cause the first control circuit to exit the low power state.
摘要翻译：公开了一种在时钟边界上传输数据时节省电力的装置和方法。在一个实施例中，一种装置包括FIFO，其耦合以从第一时钟域中的电路接收数据，并将数据输出到第二时钟域中的电路。第一个控制电路负责将数据写入FIFO。第二个控制电路负责从FIFO中读取数据。如果FIFO中的数据量超过第一阈值，则电源管理电路可以将第一控制电路置于低功率状态。第二控制电路可以监视FIFO中的数据量。如果FIFO中的数据量低于第二阈值，则它可以向电源管理电路断言一个指示。此后，电源管理电路可以使第一控制电路退出低功率状态。

97. 发明授权

US07876720B2 Method and circuit for differential clock pulse compensation between two clock-pulse systems 有权
标题翻译：两个时钟脉冲系统之间差分时钟脉冲补偿的方法和电路
公开(公告)号：US07876720B2
公开(公告)日：2011-01-25
申请号：US11463506
申请日：2006-08-09
申请人： Frank Huertgen , Bernd Schmandt
发明人： Frank Huertgen , Bernd Schmandt
IPC分类号： H04J3/06
CPC分类号： H04L25/05 , G06F5/06 , G06F2205/061 , G06F2205/126 , H04L7/005
摘要： A differential clock pulse compensation is performed between the clock-pulse system (23) of a digital line-connected data interface and the asynchronous clock-pulse system (22) of a digital wireless data interface. A characteristic variable (20, 21) for the asynchronous differential clock pulse between the clock-pulse systems (22, 23) is monitored hereby. The data rate of the data (15, 16) transmitted over the line-connected data interface is adapted depending on the characteristic variable (20, 21).
摘要翻译：在数字线路连接的数据接口的时钟脉冲系统（23）和数字无线数据接口的异步时钟脉冲系统（22）之间执行差分时钟脉冲补偿。此时监视用于时钟脉冲系统（22,23）之间的异步差分时钟脉冲的特征变量（20,21）。通过线路连接数据接口传输的数据（15,16）的数据速率根据特性变量（20,21）进行调整。

98. 发明申请

US20070260771A1 Method of Reducing Clock Differential in a Data Processing System 审中-公开
标题翻译：减少数据处理系统中时钟差分的方法
公开(公告)号：US20070260771A1
公开(公告)日：2007-11-08
申请号：US11279112
申请日：2006-04-10
申请人： Cheng-Hao Lee , Jui-Lun Chang
发明人： Cheng-Hao Lee , Jui-Lun Chang
IPC分类号： G06F3/00
CPC分类号： G06F5/06 , G06F2205/061 , G06F2205/126
摘要： A method of preventing buffer underrun and buffer overrun errors in a data processing system is disclosed. The method includes providing a reference frequency for the data processing system, storing data samples to be processed in a first in, first out (FIFO) register, detecting a level of the FIFO register for indicating how many data samples are stored in the FIFO register, dividing the reference frequency by a divisor for producing a working frequency having a lower frequency than the reference frequency, wherein the divisor is not equal to zero and the divisor is adjusted according to the level of the FIFO register, and processing the data samples stored in the FIFO register using the working frequency.
摘要翻译：公开了一种在数据处理系统中防止缓冲器欠载和缓冲器溢出错误的方法。该方法包括提供数据处理系统的参考频率，将要处理的数据样本存储在先进先出（FIFO）寄存器中，检测FIFO寄存器的电平，以指示多少数据样本存储在FIFO寄存器中将参考频率除以除数以产生具有比参考频率低的频率的工作频率，其中除数不等于零，并且除数根据FIFO寄存器的电平进行调整，并处理存储的数据样本在FIFO寄存器中使用工作频率。

99. 发明申请

US20060294267A1 Method for setting data carrier speed in a data carrier drive apparatus 审中-公开
标题翻译：用于在数据载体驱动装置中设置数据载体速度的方法
公开(公告)号：US20060294267A1
公开(公告)日：2006-12-28
申请号：US10557385
申请日：2004-05-12
申请人： Ludo Albert Lenaerts
发明人： Ludo Albert Lenaerts
IPC分类号： G06F3/00
CPC分类号： G11B19/26 , G06F5/12 , G06F2205/061
摘要： A method is described for setting a disc speed in a disc drive apparatus (3) which is in data transfer communication (7) with a host system (2), wherein data transfer between carrier and drive apparatus takes place with a carrier/drive transfer rate (DDTR) and wherein data transfer between drive apparatus and host system takes place with a drive/host transfer rate (DHTR). A target speed different from the current speed is calculated; the expected carrier/drive transfer rate (DDTRex) at the target speed is calculated; and the drive/host transfer rate (DHTR) is compared to the expected carrier/drive transfer rate (DDTRex). The current speed is maintained if said comparison between drive/host transfer rate (DHTR) and expected carrier/drive transfer rate (DDTRex) indicates that a next speed change from the said target speed back to the current speed is to be expected if the speed would be changed to the said target speed.
摘要翻译：描述了一种用于在与主机系统（2）进行数据传送通信（7）的盘驱动装置（3）中设置盘速度的方法，其中在载体和驱动装置之间的数据传送通过载波/驱动传送速率（DDTR），并且其中驱动装置和主机系统之间的数据传输以驱动/主机传输速率（DHTR）进行。计算与当前速度不同的目标速度; 计算目标速度下的预期载波/驱动传输速率（DDTRex）; 并将驱动/主机传输速率（DHTR）与预期载波/驱动器传输速率（DDTRex）进行比较。如果驱动/主机传输速率（DHTR）和预期载波/驱动器传输速率（DDTRex）之间的比较指示从所述目标速度改变到当前速度的下一个速度如果速度将改为目标速度。

100. 发明授权

US07106696B1 Systems and methods for limiting the rates of data to/from a buffer 失效
公开(公告)号：US07106696B1
公开(公告)日：2006-09-12
申请号：US09942630
申请日：2001-08-31
申请人： Raymond Marcelino Manese Lim , Song Zhang , Anurag P. Gupta , Brian Gaudet
发明人： Raymond Marcelino Manese Lim , Song Zhang , Anurag P. Gupta , Brian Gaudet
IPC分类号： G06F11/00 , H04L12/26
CPC分类号： G06F5/06 , G06F2205/061
摘要： A system controls the transfer of data. The system receives a request to transfer data and determines whether a counter value equals or exceeds a threshold. The counter value represents an amount of time since a previous data transfer. When the counter value equals or exceeds the threshold, the system transmits the data. In another implementation, the system tracks the amount of data read from a buffer. The system reduces the speed at which data is read when the amount of data read from the buffer exceeds a threshold.

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