专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US08477558B2 Memory apparatuses with low supply voltages 有权
标题翻译：具有低电源电压的存储设备
公开(公告)号：US08477558B2
公开(公告)日：2013-07-02
申请号：US12262070
申请日：2008-10-30
申请人： Jaume Abella , Xavier Vera , Javier Carretero Casado , Pedro Chaparro Monferrer , Antonio González
发明人： Jaume Abella , Xavier Vera , Javier Carretero Casado , Pedro Chaparro Monferrer , Antonio González
IPC分类号： G11C8/00
CPC分类号： G06F13/4234 , G06F12/0802 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Low supply voltage memory apparatuses are presented. In one embodiment, a memory apparatus comprises a memory and a memory controller. The memory controller includes a read controller. The read controller prevents a read operation to a memory location from being completed, for at least N clock cycles after a write operation to the memory location, where N is the number of clock cycles for the memory location to stabilize after the write operation.
摘要翻译：提供了低电压存储装置。在一个实施例中，存储器装置包括存储器和存储器控制器。存储器控制器包括读控制器。读取控制器防止对存储器位置的读取操作在对存储器位置的写入操作之后至少N个时钟周期完成，其中N是在写入操作之后存储器位置稳定的时钟周期数。

92. 发明授权

US08429356B2 Write data mask method and system 有权
标题翻译：写数据掩码的方法和系统
公开(公告)号：US08429356B2
公开(公告)日：2013-04-23
申请号：US11359809
申请日：2006-02-22
申请人： Joseph D. Macri , Stephen Morein , Ming-Ju E. Lee , Lin Chen
发明人： Joseph D. Macri , Stephen Morein , Ming-Ju E. Lee , Lin Chen
IPC分类号： G06F13/00
CPC分类号： G06F12/00 , G06F13/4234 , G06F13/4243 , G11C7/02 , G11C7/1006 , G11C7/1078 , G11C7/1096
摘要： A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.
摘要翻译：描述了用于执行字节写入的方法和系统，其中字节写入仅涉及仅写入多字节写入操作的特定字节。实施例包括指示在字节写入操作中要写入哪些字节的掩码数据。不使用专用的掩码引脚或专用掩码线。在一个实施例中，掩码数据在数据线上传输，并响应于write_mask命令存储。在一个实施例中，掩模数据作为写入命令的一部分被发送。

93. 发明申请

US20130094271A1 CONNECTION OF MULTIPLE SEMICONDUCTOR MEMORY DEVICES WITH CHIP ENABLE FUNCTION 审中-公开
标题翻译：多芯半导体存储器件与芯片启用功能的连接
公开(公告)号：US20130094271A1
公开(公告)日：2013-04-18
申请号：US13588195
申请日：2012-08-17
申请人： Roland Schuetz
发明人： Roland Schuetz
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G06F13/4234 , G06F13/4247 , G11C5/066 , G11C7/10 , G11C7/20 , G11C16/08 , G11C2216/30
摘要： A system comprising a plurality of memory devices coupled by a common bus to a controller has a single serially coupled enable signal per channel. Each memory device or chip comprises a serial enable input and enable output and a register for storing a device identifier, e.g., chip ID. The memory devices are serially coupled by a serial enable link, for assertion of a single enable signal to all devices. This parallel data and serial enable configuration provides reduced per-channel pin count, relative to conventional systems that require a unique enable signal for each device. In operation, commands on the common bus targeting an individual device are asserted by adding an address field comprising a device identifier to each command string, preferably in an initial identification cycle of the command. Methods are also disclosed for initializing the system, comprising assigning device identifiers and obtaining a device count, prior to normal operation.
摘要翻译：包括通过公共总线耦合到控制器的多个存储器件的系统具有每个通道的单个串联耦合使能信号。每个存储器件或芯片包括串行使能输入和使能输出以及用于存储器件标识符（例如芯片ID）的寄存器。存储器件通过串行使能链路串联耦合，用于断言所有器件的单个使能信号。相对于需要每个器件的唯一使能信号的传统系统，这种并行数据和串行使能配置提供减少的每通道引脚数。在操作中，通过将优选地在命令的初始识别周期中添加包括设备标识符的地址字段到每个命令串来断言公共总线上针对单个设备的命令被断言。还公开了用于初始化系统的方法，包括在正常操作之前分配设备标识符并获得设备计数。

94. 发明授权

US08321650B2 Alignment-unit-based virtual formatting methods and devices employing the methods 有权
标题翻译：基于对齐单元的虚拟格式化方法和采用该方法的设备
公开(公告)号：US08321650B2
公开(公告)日：2012-11-27
申请号：US11986959
申请日：2007-11-26
申请人： Joseph H. Steinmetz , Murthy Kompella , Narayan Ayalasomayajula , Donia Sebastian
发明人： Joseph H. Steinmetz , Murthy Kompella , Narayan Ayalasomayajula , Donia Sebastian
IPC分类号： G06F12/00
CPC分类号： G06F13/4234 , G06F3/0607 , G06F3/0611 , G06F3/0617 , G06F3/0626 , G06F3/064 , G06F3/0658 , G06F3/0661 , G06F3/0689 , G06F11/201 , G06F11/2089 , H04L67/1097
摘要： In various embodiments, the present invention provides virtual disk formatting by intermediate devices including: (1) a storage shelf router and the storage shelf in which the storage-shelf is included, to external computing entities, such as disk-array controllers and host computers; (2) an I/O controller; and (3) a storage-bridge device. Additional embodiments of the present invention enhance virtual formatting by using additional padding, in a dual-abstraction method, to efficiently align virtual-block reads with underlying device blocks. Yet additional embodiments of the present invention allow for tracking and correcting device blocks corrupted during READ-MODIFY operations that occur during virtual-block WRITE operations. Various intermediate devices may employ two or more of the virtual formatting, dual abstraction, and corrupted-device-block tracking methods.
摘要翻译：在各种实施例中，本发明提供了由中间设备提供的虚拟磁盘格式化，包括：（1）存储架路由器和其中包含存储架的存储架，到诸如磁盘阵列控制器和主计算机之类的外部计算实体 ; （2）I / O控制器; 和（3）存储桥装置。本发明的另外的实施例通过在双抽象方法中使用附加填充来有效地将虚拟块读取与底层设备块对齐来增强虚拟格式化。本发明的另外的实施例允许跟踪和校正在虚拟块写入操作期间发生的READ-MODIFY操作期间损坏的设备块。各种中间设备可以采用虚拟格式化，双重抽象和损坏设备块跟踪方法中的两个或多个。

95. 发明授权

US08266369B2 Flash memory interface 有权
标题翻译：闪存接口
公开(公告)号：US08266369B2
公开(公告)日：2012-09-11
申请号：US12642133
申请日：2009-12-18
申请人： Craig MacKenna , Prithvi Nagaraj , Rob Cosaro
发明人： Craig MacKenna , Prithvi Nagaraj , Rob Cosaro
IPC分类号： G06F12/00 , G06F13/16 , G06F13/40 , G06F13/42
CPC分类号： G06F13/4234
摘要： Flash-type memory access and control is facilitated (e.g., as random-access memory). According to an example embodiment, an interface communicates with and controls a flash memory circuit over a peripheral interface bus. The interface uses a FIFO buffer coupled to receive data from and store data for the flash memory circuit and to provide access to the stored data. An interface controller communicates with the flash memory circuit via the peripheral interface bus to initialize the flash memory circuit and to access data thereto, in response to requests from a processor. In some applications, the flash memory circuit is initialized by sending commands to it. The interface may be placed into a read-only mode in which data in the flash memory is accessed as part of main (computer) processor memory, using the FIFO to buffer data from the flash.
摘要翻译：闪存型存储器访问和控制被促进（例如，作为随机存取存储器）。根据示例实施例，接口通过外围接口总线与快闪存储器电路通信并控制闪存电路。该接口使用FIFO缓冲器，其耦合以从闪存电路接收数据并存储数据，并提供对存储的数据的访问。接口控制器通过外围接口总线与闪速存储器电路进行通信，以响应于来自处理器的请求来初始化闪存电路并访问数据。在某些应用中，通过向其发送命令来初始化闪存电路。接口可以被置于只读模式，其中闪存中的数据作为主（计算机）处理器存储器的一部分被访问，使用FIFO来缓冲闪存中的数据。

96. 发明申请

US20120198155A1 PORTABLE DATA CARRIER HAVING ADDITIONAL FUNCTIONALITY 有权
标题翻译：便携式数据载体具有附加功能
公开(公告)号：US20120198155A1
公开(公告)日：2012-08-02
申请号：US13500108
申请日：2010-10-04
申请人： Axel Heider
发明人： Axel Heider
IPC分类号： G06F12/00
CPC分类号： G06F13/4234 , G06F12/0246 , G06F13/385 , G06F21/71 , G06F21/72 , G06F21/79
摘要： In a method in a portable data carrier for executing an additional functionality in the data carrier, whereby the data carrier comprises a memory and whereby the additional functionality is called up by means of the one access of a conventional read command ordered from outside the data carrier to the memory of the data carrier, the additional functionality is further specified by a respective further access of at least one further conventional read command to the memory of the data carrier.
摘要翻译：在用于在数据载体中执行附加功能的便携式数据载体中的方法中，由此数据载体包括存储器，由此通过从数据载体外部排序的常规读取命令的一次访问调用附加功能对于数据载体的存储器，通过至少一个另外的常规读取命令对数据载体的存储器的相应进一步访问进一步指定附加功能。

97. 发明申请

US20120195350A1 System and Method for Facilitating Data Transfer Using a Shared Non-Deterministic Bus 有权
标题翻译：使用共享非确定性总线促进数据传输的系统和方法
公开(公告)号：US20120195350A1
公开(公告)日：2012-08-02
申请号：US13186391
申请日：2011-07-19
申请人： Srinjoy Das , Philip Crary , Alexander Raykhman
发明人： Srinjoy Das , Philip Crary , Alexander Raykhman
IPC分类号： H04L27/00 , H04B1/707
CPC分类号： G06F13/1626 , G06F13/1605 , G06F13/1663 , G06F13/18 , G06F13/4059 , G06F13/4234 , G11C7/1039
摘要： System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
摘要翻译：根据各种条件促进逻辑系统与存储器之间的数据传输的系统和方法。实施例包括用于促进和改善使用共享非确定性总线的数据传输的吞吐量的系统和方法，用于管理作为循环缓冲器的存储器的系统和方法，以及用于促进第一时钟域和第二时钟域之间的数据传输的系统和方法第二个时钟域。实施例可以单独地或组合地实现。

98. 发明授权

US08214570B2 Memory controller and method utilizing equalization co-efficient setting 有权
标题翻译：存储器控制器和方法利用均衡系统设置
公开(公告)号：US08214570B2
公开(公告)日：2012-07-03
申请号：US13196840
申请日：2011-08-02
申请人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
发明人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： G06F13/00
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： A chip includes a transmitter circuit and a register provided to store a value representative of an equalization co-efficient setting. The transmitter circuit includes an output driver configured to adjust an output data signal based at least in part on the equalization co-efficient setting.
摘要翻译：一个芯片包括一个发射机电路和一个寄存器，用于存储代表均衡系统设置的值。发射机电路包括输出驱动器，其被配置为至少部分地基于均衡系数设置来调整输出数据信号。

99. 发明申请

US20120110397A1 DATA TRANSMISSION SYSTEM, STORAGE MEDIUM AND DATA TRANSMISSION PROGRAM 有权
标题翻译：数据传输系统，存储介质和数据传输程序
公开(公告)号：US20120110397A1
公开(公告)日：2012-05-03
申请号：US13234564
申请日：2011-09-16
申请人： Shingo Tanaka , Takahiro Yamaura
发明人： Shingo Tanaka , Takahiro Yamaura
IPC分类号： G06F11/08 , G06F13/42
CPC分类号： G06F13/4234 , H04L2001/0094 , Y02D10/14 , Y02D10/151
摘要： A system has a processor configured to be capable of read and write to a main memory, a storage configured to transmit stored data per block on an I/O bus, and a protocol processing apparatus connected to the I/O bus and configured to perform a communication protocol process on behalf of the processor. The processor includes a specifying part configured to specify data per block to be transmitted from the storage, and an indicating part configured to indicate data transfer from the storage to the protocol processing apparatus by specifying address information of the protocol processing apparatus. The protocol processing apparatus includes a receiving part configured to directly receive data transferred per block from the storage to the I/O bus, without relaying the main memory, and a network processing part configured to transmit the data received per block by the receiving part over a network per packet.
摘要翻译：一种系统具有被配置为能够读取和写入主存储器的处理器，被配置为在I / O总线上每块发送存储的数据的存储器，以及连接到I / O总线并被配置为执行的协议处理装置代表处理器的通信协议过程。处理器包括指定部，被配置为指定要从存储发送的每个块的数据;以及指示部，被配置为指示通过指定协议处理装置的地址信息从存储器向协议处理装置的数据传送。该协议处理装置包括接收部件，被配置为直接从每个块传输的数据从存储器传送到I / O总线，而不中继主存储器;以及网络处理部件，被配置为将每个块接收的数据由接收部件发送每个数据包的网络。

100. 发明申请

US20120072682A1 DETECTION CIRCUIT FOR MIXED ASYNCHRONOUS AND SYNCHRONOUS MEMORY OPERATION 有权
标题翻译：用于混合异步和同步存储器操作的检测电路
公开(公告)号：US20120072682A1
公开(公告)日：2012-03-22
申请号：US13308333
申请日：2011-11-30
申请人： Simon J. Lovett
发明人： Simon J. Lovett
IPC分类号： G06F12/00
CPC分类号： G06F13/4234 , G06F13/1689 , G06F13/1694 , G06F13/4243 , G11C7/1045 , G11C7/1072 , G11C11/406 , G11C11/40615 , G11C11/4076 , G11C11/413
摘要： A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.
摘要翻译：一种存储器访问模式检测电路和方法，用于检测和启动存储器件的存储器访问模式存储器访问模式检测电路接收存储器地址信号，控制信号和时钟信号，并响应于接收产生第一模式检测信号的存储器地址信号或控制信号的第一组合。在检测信号之后产生第一模式启动信号，以启动第一模式存储器访问操作。响应于接收到控制信号和活动时钟信号的第二组合，存储器访问模式检测电路还产生第二模式检测信号以启动第二模式存储器访问操作并且抑制第一模式检测信号的产生，从而取消第一模式存储器存取操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式