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91. 发明申请

US20130054853A1 Method and Apparatus for Load-Based Prefetch Access 有权
标题翻译：基于负载的预取访问方法和装置
公开(公告)号：US20130054853A1
公开(公告)日：2013-02-28
申请号：US13222399
申请日：2011-08-31
申请人： Feng Wang , Jonghae Kim
发明人： Feng Wang , Jonghae Kim
IPC分类号： G06F13/00
CPC分类号： G06F13/161 , G06F13/1652 , Y02D10/14
摘要： A load state of a slave memory is detected and provided to a master device. The master device communicates prefetch access requests to the slave memory based, at least in part, on the detected load state. Optionally, the master device communicates prefetch requests to the slave memory according to a schedule based, at least in part, on the detected load state.
摘要翻译：从存储器的负载状态被检测并提供给主设备。至少部分地基于检测到的负载状态，主设备将预取访问请求传送到从属存储器。可选地，主设备至少部分地基于检测到的负载状态，根据调度将预取请求传送到从存储器。

92. 发明申请

US20120310621A1 PROCESSOR, DATA PROCESSING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE PROCESSOR 审中-公开
标题翻译：处理器，其数据处理方法，以及包括处理器的存储器系统
公开(公告)号：US20120310621A1
公开(公告)日：2012-12-06
申请号：US13474942
申请日：2012-05-18
申请人： SEH WOONG JEONG , Jae Sop Kong
发明人： SEH WOONG JEONG , Jae Sop Kong
IPC分类号： G06F9/455 , G06F12/00
CPC分类号： G06F13/161 , G06F13/105
摘要： A processor includes an emulator configured to receive an access command from a second memory controller, and a first memory controller configured to control an operation of a memory. The emulator is configured to determine whether the first memory controller is available to perform an operation corresponding to the access command, and transmit a wait signal to the second memory controller upon determining that the first memory controller is not available to perform the operation.
摘要翻译：处理器包括被配置为从第二存储器控制器接收访问命令的仿真器和被配置为控制存储器的操作的第一存储器控制器。仿真器被配置为确定第一存储器控制器是否可用于执行与访问命令相对应的操作，并且在确定第一存储器控制器不可用于执行操作时将等待信号发送到第二存储器控制器。

93. 发明授权

US08285892B2 Quantum burst arbiter and memory controller 有权
标题翻译：量子突发仲裁器和存储器控制器
公开(公告)号：US08285892B2
公开(公告)日：2012-10-09
申请号：US12857716
申请日：2010-08-17
申请人： Eskild T. Arntzen , Sheri L. Fredenberg , Jackson L. Ellis , Robert W. Warren
发明人： Eskild T. Arntzen , Sheri L. Fredenberg , Jackson L. Ellis , Robert W. Warren
IPC分类号： G06F13/28
CPC分类号： G06F13/1684 , G06F13/161
摘要： An apparatus comprising an arbiter circuit, a protocol engine circuit and a channel router circuit. The arbiter circuit may be configured to determine a winning channel from a plurality of channel requests based on a first criteria. Each of the plurality of channel requests may represent a burst of data having a fixed length aligned to an address boundary of a memory. The protocol engine circuit may be configured to receive a signal from the arbiter circuit indicating the winning channel. The protocol engine circuit may also be configured to perform a memory protocol at a granularity equal to the burst of data. The channel router circuit may be configured to present the plurality of channel requests to the arbiter circuit and the protocol engine circuit.
摘要翻译：一种包括仲裁器电路，协议引擎电路和信道路由器电路的装置。仲裁器电路可以被配置为基于第一准则从多个信道请求中确定获胜信道。多个信道请求中的每一个可以表示具有与存储器的地址边界对准的固定长度的数据突发。协议引擎电路可以被配置为从仲裁器电路接收指示获胜信道的信号。协议引擎电路还可以被配置为以等于数据突发的粒度执行存储器协议。信道路由器电路可以被配置为向仲裁器电路和协议引擎电路呈现多个信道请求。

94. 发明申请

US20120239885A1 MEMORY HUB WITH INTERNAL CACHE AND/OR MEMORY ACCESS PREDICTION 失效
标题翻译：具有内部缓存和/或内存访问预测的存储器总线
公开(公告)号：US20120239885A1
公开(公告)日：2012-09-20
申请号：US13487445
申请日：2012-06-04
申请人： Joseph M. Jeddeloh
发明人： Joseph M. Jeddeloh
IPC分类号： G06F12/08
CPC分类号： G06F12/0866 , G06F12/0862 , G06F12/0893 , G06F13/161
摘要： A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address.
摘要翻译：计算机系统包括用于将处理器耦合到多个同步动态随机存取存储器（“SDRAM”）设备的存储器集线器。存储器集线器包括耦合到处理器的处理器接口和耦合到各个SDRAM器件的多个存储器接口。处理器接口通过交换机耦合到存储器接口。每个存储器接口包括存储器控制器，高速缓冲存储器和预测单元。高速缓冲存储器存储最近从相应的SDRAM器件读取或写入相应SDRAM器件的数据，使得其随后可以以相对较小的延迟被处理器读取。预测单元基于先前访问的地址从可能读取访问的地址预取数据。

95. 发明授权

US08250197B2 Quality of service management 有权
标题翻译：服务质量管理
公开(公告)号：US08250197B2
公开(公告)日：2012-08-21
申请号：US12260041
申请日：2008-10-28
申请人： Ajay Gulati , Irfan Ahmad
发明人： Ajay Gulati , Irfan Ahmad
IPC分类号： G06F15/173 , G06F13/28 , G06F9/46
CPC分类号： H04L47/56 , G06F3/0659 , G06F13/161 , G06F2213/0064 , H04L1/0018 , H04L29/08099 , H04L49/90 , H04L49/901 , H04L65/601 , H04L65/80 , H04L67/1097 , H04L67/2809
摘要： A method for providing quality of service to a plurality of hosts accessing a common resource is described. The common resource may be a middle-tier or back-end server. A client IO request is received at one host of the plurality of hosts from one of a plurality clients executing as software entities on respective hosts. The host determines whether an issue queue is full. The IO request is issued to the common resource when the issue queue is not full. A current average latency observed at the host and an adjusted window size is calculated, based at least in part on the current average latency. The issue queue is resized to correspond with the adjusted window size.
摘要翻译：描述了向访问公共资源的多个主机提供服务质量的方法。公共资源可能是中间层或后端服务器。在多个客户端中的一个主机上从在相应主机上作为软件实体执行的多个客户端之一接收客户端IO请求。主机确定问题队列是否已满。当问题队列未满时，IO请求将发布到公共资源。至少部分地基于当前的平均延迟来计算在主机处观察到的当前平均延迟和调整的窗口大小。调整问题队列大小以调整窗口大小。

96. 发明申请

US20120210055A1 Controlling latency and power consumption in a memory 有权
标题翻译：控制内存中的延迟和功耗
公开(公告)号：US20120210055A1
公开(公告)日：2012-08-16
申请号：US13317245
申请日：2011-10-13
申请人： Timothy Charles Mace , Ashley John Crawford
发明人： Timothy Charles Mace , Ashley John Crawford
IPC分类号： G06F12/00
CPC分类号： G06F13/1626 , G06F1/3225 , G06F13/161
摘要： Memory circuitry, a data processing apparatus and a method of storing data are disclosed. The memory circuitry comprises: a memory for storing the data; and control circuitry for controlling power consumption of the memory by controlling a rate of access to the memory such that an average access delay between adjacent accesses is maintained at or above a predetermined value; wherein the control circuitry is configured to determine a priority of an access request to the memory and to maintain the average access delay at or above the predetermined value by delaying at least some accesses from access requests having a lower priority for longer than at least some accesses from access requests having a higher priority.
摘要翻译：公开了存储器电路，数据处理装置和存储数据的方法。存储器电路包括：用于存储数据的存储器; 以及控制电路，用于通过控制对存储器的访问速率来控制存储器的功耗，使得相邻访问之间的平均访问延迟保持在或超过预定值; 其中所述控制电路被配置为确定对所述存储器的访问请求的优先级，并且通过将具有较低优先权的访问请求的至少一些访问延迟至少比至少一些访问更长的时间来将所述平均访问延迟维持在或高于所述预定值来自具有较高优先级的访问请求。

97. 发明授权

US08195918B2 Memory hub with internal cache and/or memory access prediction 有权
标题翻译：具有内部缓存和/或内存访问预测的内存集线器
公开(公告)号：US08195918B2
公开(公告)日：2012-06-05
申请号：US13108405
申请日：2011-05-16
申请人： Joseph M. Jeddeloh
发明人： Joseph M. Jeddeloh
IPC分类号： G06F12/08 , G06F13/16
CPC分类号： G06F12/0866 , G06F12/0862 , G06F12/0893 , G06F13/161
摘要： A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address.
摘要翻译：计算机系统包括用于将处理器耦合到多个同步动态随机存取存储器（“SDRAM”）设备的存储器集线器。存储器集线器包括耦合到处理器的处理器接口和耦合到各个SDRAM器件的多个存储器接口。处理器接口通过交换机耦合到存储器接口。每个存储器接口包括存储器控制器，高速缓冲存储器和预测单元。高速缓冲存储器存储最近从相应的SDRAM器件读取或写入相应SDRAM器件的数据，使得其随后可以以相对较小的延迟被处理器读取。预测单元基于先前访问的地址从可能读取访问的地址预取数据。

98. 发明申请

US20120011331A1 MEMORY SYSTEM, CONTROLLER AND DEVICE THAT SUPPORTS A MERGED MEMORY COMMAND PROTOCOL 审中-公开
标题翻译：记忆系统，控制器和设备，支持合并记忆命令协议
公开(公告)号：US20120011331A1
公开(公告)日：2012-01-12
申请号：US13141881
申请日：2010-03-10
申请人： Frederick A. Ware , John Welsford Brooks , Kishore Ven Kasamsetty , Richard E. Perego
发明人： Frederick A. Ware , John Welsford Brooks , Kishore Ven Kasamsetty , Richard E. Perego
IPC分类号： G06F12/00
CPC分类号： G06F13/161
摘要： The present embodiments provide a memory system which is configured to send a request from a memory controller to a memory device, wherein the request includes independent activate and precharge commands. The activate command is associated with a row address, which identifies a first row for the activate command. In response to the activate command, the system activates the first row in a first bank in the memory device. Similarly, in response to the precharge command, the system precharges a second bank in the memory device.
摘要翻译：本实施例提供了一种被配置为从存储器控制器向存储器件发送请求的存储器系统，其中该请求包括独立的激活和预充电命令。 activate命令与行地址相关联，该行地址标识了activate命令的第一行。响应于激活命令，系统激活存储器设备中的第一组中的第一行。类似地，响应于预充电命令，系统对存储器件中的第二存储体进行预充电。

99. 发明申请

US20110314231A1 BANDWIDTH ADAPTIVE MEMORY COMPRESSION 有权
标题翻译： BANDWIDTH自适应内存压缩
公开(公告)号：US20110314231A1
公开(公告)日：2011-12-22
申请号：US12820300
申请日：2010-06-22
申请人： James Michael O'Connor
发明人： James Michael O'Connor
IPC分类号： G06F12/00
CPC分类号： G06F13/161 , G06F12/04 , G06F13/1694
摘要： Data is retrieved from system memory in compressed mode if a determination is made that the memory bus is bandwidth limited and in uncompressed mode if the memory bus is not bandwidth limited. Determination of the existence of the bandwidth limited condition may be based on memory bus utilization or according to a depth of a queue of memory access requests.
摘要翻译：如果确定存储器总线是带宽限制的，并且如果存储器总线不受带宽限制，则在未压缩模式下，以压缩模式从系统存储器检索数据。确定带宽限制条件的存在可以基于存储器总线利用率或根据存储器访问请求队列的深度。

100. 发明授权

US08069274B2 System and method for serial data communications between host and communications devices, and communications device employed in the system and method 有权
标题翻译：用于主机和通信设备之间串行数据通信的系统和方法，以及系统和方法中使用的通信设备
公开(公告)号：US08069274B2
公开(公告)日：2011-11-29
申请号：US12510390
申请日：2009-07-28
申请人： Yohsuke Fukuda , Kazuhiko Hara
发明人： Yohsuke Fukuda , Kazuhiko Hara
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/161
摘要： A communications device includes a communications circuit, a memory, an identifier generator, and a latency controller. The communications circuit exchanges serial data with a host computer and a downstream device, and includes a first input, a first output, a second input, and a second output. The first input receives data from the host computer. The first output transmits data to the host computer. The second input receives data from the downstream device. The second output transmits data to the downstream device. The memory is accessible through the communications circuit. The identifier generator generates an identifier number unique to the communications device in response to an identifier setup request received at the first input. The latency controller determines, based on the generated identifier number, a period of latency required to access the memory through the communications circuit.
摘要翻译：通信设备包括通信电路，存储器，标识符发生器和等待时间控制器。通信电路与主机和下游设备交换串行数据，并且包括第一输入，第一输出，第二输入和第二输出。第一个输入从主机接收数据。第一个输出将数据传输到主机。第二个输入从下游设备接收数据。第二个输出将数据发送到下游设备。存储器可通过通信电路访问。响应于在第一输入处接收到的标识符建立请求，标识符生成器生成通信设备唯一的标识符号。等待时间控制器基于生成的标识符号确定通过通信电路访问存储器所需的等待时间。

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