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    • 1. 发明授权
    • System and method for serial data communications between host and communications devices, and communications device employed in the system and method
    • 用于主机和通信设备之间串行数据通信的系统和方法,以及系统和方法中使用的通信设备
    • US08069274B2
    • 2011-11-29
    • US12510390
    • 2009-07-28
    • Yohsuke FukudaKazuhiko Hara
    • Yohsuke FukudaKazuhiko Hara
    • G06F3/00G06F13/00
    • G06F13/161
    • A communications device includes a communications circuit, a memory, an identifier generator, and a latency controller. The communications circuit exchanges serial data with a host computer and a downstream device, and includes a first input, a first output, a second input, and a second output. The first input receives data from the host computer. The first output transmits data to the host computer. The second input receives data from the downstream device. The second output transmits data to the downstream device. The memory is accessible through the communications circuit. The identifier generator generates an identifier number unique to the communications device in response to an identifier setup request received at the first input. The latency controller determines, based on the generated identifier number, a period of latency required to access the memory through the communications circuit.
    • 通信设备包括通信电路,存储器,标识符发生器和等待时间控制器。 通信电路与主机和下游设备交换串行数据,并且包括第一输入,第一输出,第二输入和第二输出。 第一个输入从主机接收数据。 第一个输出将数据传输到主机。 第二个输入从下游设备接收数据。 第二个输出将数据发送到下游设备。 存储器可通过通信电路访问。 响应于在第一输入处接收到的标识符建立请求,标识符生成器生成通信设备唯一的标识符号。 等待时间控制器基于生成的标识符号确定通过通信电路访问存储器所需的等待时间。
    • 2. 发明授权
    • DC offset cancel control method and transmitter/receiver
    • 直流偏移消除控制方法和发射机/接收机
    • US07664478B2
    • 2010-02-16
    • US11364328
    • 2006-03-01
    • Yohsuke Fukuda
    • Yohsuke Fukuda
    • H04B1/10
    • H04B1/30
    • Disclosed is a transmitter/receiver which performs transmitting and receiving operations based on CSMA/CA (Carrier Sense Multiple Access with Collision Avoidance) system. The transmitter/receiver includes a first unit, a second unit and a DC offset control unit. The first unit obtains a DC offset value generated in the transmitter/receiver and holds the obtained DC offset value. The second unit removes the held DC offset value from received data. The DC offset control unit causses the first unit to operate upon response to at least one of transmission completion and reception completion.
    • 公开了一种基于CSMA / CA(具有冲突避免的载波侦听多路访问)系统进行发送和接收操作的发射机/接收机。 发射机/接收机包括第一单元,第二单元和直流偏移控制单元。 第一单元获得在发送器/接收器中产生的DC偏移值,并保持所获得的DC偏移值。 第二个单元从接收到的数据中删除保持的DC偏移值。 DC偏移控制单元通过响应于传输完成和接收完成中的至少一个来使第一单元起作用。
    • 5. 发明授权
    • Error diffusion processing circuit
    • 误差扩散处理电路
    • US08699792B2
    • 2014-04-15
    • US13336804
    • 2011-12-23
    • Yohsuke Fukuda
    • Yohsuke Fukuda
    • G06K9/00
    • H04N1/4053H04N1/40062
    • An error diffusion processing circuit includes a memory having a predetermined size in which (P−1)×M dithering threshold matrices in a predetermined size for each of the quantization thresholds and color components are pre-stored, and a quantization threshold selector configured to select (P−1) matrices for the color component of the target pixel data from the dithering threshold matrices stored in the memory, and read an element from the elements of the selected matrices in accordance with a pixel position of the target pixel data in the image data for output as the (P−1) quantization thresholds. P is an integer of 2 or more and M is a positive integer. The data size of the dithering threshold matrices is set to be equal to or less than a value obtained by dividing a size of the memory by the number of dithering threshold matrices.
    • 误差扩散处理电路包括具有预定尺寸的存储器,其中针对每个量化阈值和颜色分量预先存储预定尺寸的(P-1)×M个抖动阈值矩阵,以及量化阈值选择器,被配置为选择 (P-1)矩阵,用于根据存储在存储器中的抖动阈值矩阵的目标像素数据的颜色分量,并且根据图像中的目标像素数据的像素位置从所选择的矩阵的元素中读取元素 作为(P-1)量化阈值的输出数据。 P是2以上的整数,M是正整数。 将抖动阈值矩阵的数据大小设置为等于或小于通过将存储器的大小除以抖动阈值矩阵的数量而获得的值。
    • 6. 发明申请
    • MEMORY ACCESS CONTROLLER, SYSTEM, AND METHOD
    • 存储器访问控制器,系统和方法
    • US20100138578A1
    • 2010-06-03
    • US12628633
    • 2009-12-01
    • Yohsuke Fukuda
    • Yohsuke Fukuda
    • G06F13/362G06F12/00
    • G06F13/364
    • A memory access controller including a command analysis unit to receive write access request and command data and to analyze access to a memory, a command execution unit to output command and data control signals to the memory based on write data, and the analysis result, a mode setting unit to switch between a first operation mode in which a write access request is issued when both the command data and the corresponding write data are available, and a second operation mode in which a write access request is issued when the command data is available independently of availability of the write data corresponding to the command data, and a timing arbitration unit provided for each bus master to output the write access request and command data to the command analysis unit and output the write data to the command execution unit in accordance with the mode setting unit.
    • 一种存储器访问控制器,包括:命令分析单元,用于接收写访问请求和命令数据并分析对存储器的访问;命令执行单元,用于基于写入数据向存储器输出命令和数据控制信号;以及分析结果, 模式设置单元,用于在命令数据和相应的写入数据两者都可用时在其中发出写入访问请求的第一操作模式之间切换;以及第二操作模式,其中当命令数据可用时发出写访问请求 独立于对应于命令数据的写入数据的可用性,以及为每个总线主机提供的定时仲裁单元,以将写入访问请求和命令数据输出到命令分析单元,并根据命令执行单元将写入数据输出到命令执行单元 模式设置单元。
    • 7. 发明授权
    • Memory access controller, system, and method
    • 内存访问控制器,系统和方法
    • US08301816B2
    • 2012-10-30
    • US12628633
    • 2009-12-01
    • Yohsuke Fukuda
    • Yohsuke Fukuda
    • G06F13/00G06F12/00
    • G06F13/364
    • A memory access controller including a command analysis unit to receive write access request and command data and to analyze access to a memory, a command execution unit to output command and data control signals to the memory based on write data, and the analysis result, a mode setting unit to switch between a first operation mode in which a write access request is issued when both the command data and the corresponding write data are available, and a second operation mode in which a write access request is issued when the command data is available independently of availability of the write data corresponding to the command data, and a timing arbitration unit provided for each bus master to output the write access request and command data to the command analysis unit and output the write data to the command execution unit in accordance with the mode setting unit.
    • 一种存储器访问控制器,包括:命令分析单元,用于接收写访问请求和命令数据并分析对存储器的访问;命令执行单元,用于基于写入数据向存储器输出命令和数据控制信号;以及分析结果, 模式设置单元,用于在命令数据和相应的写入数据两者都可用时在其中发出写入访问请求的第一操作模式之间切换;以及第二操作模式,其中当命令数据可用时发出写访问请求 独立于对应于命令数据的写入数据的可用性,以及为每个总线主机提供的定时仲裁单元,以将写入访问请求和命令数据输出到命令分析单元,并根据命令执行单元将写入数据输出到命令执行单元 模式设置单元。
    • 8. 发明申请
    • DC offset cancel control method and transmitter/receiver
    • 直流偏移消除控制方法和发射机/接收机
    • US20060205351A1
    • 2006-09-14
    • US11364328
    • 2006-03-01
    • Yohsuke Fukuda
    • Yohsuke Fukuda
    • H04B1/00H04B1/10H04B15/00
    • H04B1/30
    • Disclosed is a transmitter/receiver which performs transmitting and receiving operations based on CSMA/CA (Carrier Sense Multiple Access with Collision Avoidance) system. The transmitter/receiver includes a first unit, a second unit and a DC offset control unit. The first unit obtains a DC offset value generated in the transmitter/receiver and holds the obtained DC offset value. The second unit removes the held DC offset value from received data. The DC offset control unit causses the first unit to operate upon response to at least one of transmission completion and reception completion.
    • 公开了一种基于CSMA / CA(具有冲突避免的载波侦听多路访问)系统进行发送和接收操作的发射机/接收机。 发射机/接收机包括第一单元,第二单元和直流偏移控制单元。 第一单元获得在发送器/接收器中产生的DC偏移值,并保持所获得的DC偏移值。 第二个单元从接收到的数据中删除保持的DC偏移值。 DC偏移控制单元通过响应于传输完成和接收完成中的至少一个来使第一单元起作用。