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91. 发明申请

US20130326263A1 DYNAMICALLY ALLOCATABLE MEMORY ERROR MITIGATION 有权
标题翻译：动态的内存不正确的缓解
公开(公告)号：US20130326263A1
公开(公告)日：2013-12-05
申请号：US13485474
申请日：2012-05-31
申请人： Alaa R. Alameldeen , Ilya Wagner , Zeshan A. Chishti , Wei Wu , Christopher B. Wilkerson
发明人： Alaa R. Alameldeen , Ilya Wagner , Zeshan A. Chishti , Wei Wu , Christopher B. Wilkerson
IPC分类号： G06F11/20
CPC分类号： G06F11/27 , G06F11/1048 , G06F11/2205
摘要： Embodiments include a method and system of dynamically allocatable memory error mitigation. In one embodiment, a system applies an error mitigation mechanism to one of multiple groups of memory units, wherein the one group is in active use during an error test of a second group of memory units. The system deactivates and tests the second group of memory units for errors. In response to detecting an error in a memory unit of the second group, the system applies, to the memory unit of the second group having the error, the error mitigation mechanism for active use. The system then activates the second group of memory units with the error mitigation mechanism applied to the memory unit of the second group having the error.
摘要翻译：实施例包括动态可分配的存储器错误缓解的方法和系统。在一个实施例中，系统将错误缓解机制应用于多组存储器单元中的一组，其中在第二组存储器单元的错误测试期间，一组正在使用。系统停用并测试第二组存储器单元的错误。响应于检测到第二组的存储器单元中的错误，系统向具有错误的第二组的存储器单元应用用于主动使用的错误减轻机制。然后，该系统激活第二组存储器单元，其中将误差减轻机制应用于具有该错误的第二组的存储器单元。

92. 发明授权

US08589750B2 Methods and apparatus for providing a built-in self test 有权
标题翻译：提供内置自检的方法和设备
公开(公告)号：US08589750B2
公开(公告)日：2013-11-19
申请号：US12836462
申请日：2010-07-14
申请人： Gaurab Banerjee , Manas Behera , Kenneth Charles Barnett
发明人： Gaurab Banerjee , Manas Behera , Kenneth Charles Barnett
IPC分类号： H03M13/00
CPC分类号： G01R31/3187 , G06F11/27
摘要： A built-in self test (BiST) system is described. The BiST system includes a circuit-under-test. The BiST system also includes one or more embedded sensors. Each of the embedded sensors includes one or more switches connected to one or more nodes within the circuit-under-test. The BiST system further includes a signal generator. The BiST system also includes a bus interface. The bus interface provides for external access of the BiST system.
摘要翻译：描述了内置的自检（BiST）系统。 BiST系统包括一个电路不足测试。 BiST系统还包括一个或多个嵌入式传感器。每个嵌入式传感器包括连接到被测电路中的一个或多个节点的一个或多个开关。 BiST系统还包括信号发生器。 BiST系统还包括总线接口。总线接口提供BiST系统的外部访问。

93. 发明授权

US08549368B1 Memory built-in-self testing in multi-core integrated circuit 有权
标题翻译：多内核集成电路内存内置自检
公开(公告)号：US08549368B1
公开(公告)日：2013-10-01
申请号：US13475948
申请日：2012-05-19
申请人： Amar Nath Deogharia , Ankush Srivastava
发明人： Amar Nath Deogharia , Ankush Srivastava
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C29/1201 , G01R31/318555 , G06F11/27 , G11C29/48 , G11C2029/0401
摘要： A multi-core integrated circuit includes first and second sets of processor cores and corresponding first and second test access ports (TAPs). The first and second TAPs are connected to corresponding first and second debug ports by way of corresponding first and second TAP controllers. The first and second sets of processor cores include first and second memory blocks and corresponding first and second built-in-self-testing (BIST) engines of different architectures. A control circuit configures the first and second TAP controllers and the connection between the first and second sets of processor cores and the first and second debug ports, for initiating the first and second BIST engines for testing the memory blocks using a predetermined test mode. A debug access module provides secure access to the first and second debug ports.
摘要翻译：多核集成电路包括第一和第二组处理器核心和相应的第一和第二测试访问端口（TAP）。第一和第二TAP通过对应的第一和第二TAP控制器连接到对应的第一和第二调试端口。第一和第二组处理器核心包括不同架构的第一和第二存储器块以及对应的第一和第二内置自测试（BIST）引擎。控制电路配置第一和第二TAP控制器以及第一和第二组处理器核与第一和第二调试端口之间的连接，用于启动第一和第二BIST引擎以使用预定测试模式来测试存储器块。调试访问模块提供对第一和第二调试端口的安全访问。

94. 发明申请

US20130191695A1 IMPLEMENTING ENHANCED PSEUDO RANDOM PATTERN GENERATORS WITH HIERARCHICAL LINEAR FEEDBACK SHIFT REGISTERS (LFSRs) 有权
标题翻译：实现具有分层线性反馈移位寄存器（LFSR）的增强型PSEUDO随机模式发生器
公开(公告)号：US20130191695A1
公开(公告)日：2013-07-25
申请号：US13353727
申请日：2012-01-19
申请人： Steven M. Douskey , Ryan A. Fitch , Michael J. Hamilton , Amanda R. Kaufer
发明人： Steven M. Douskey , Ryan A. Fitch , Michael J. Hamilton , Amanda R. Kaufer
IPC分类号： G06F11/27
CPC分类号： G06F11/27 , G01R31/318385
摘要： A method and circuit for implementing enhanced Logic Built In Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. A plurality of pseudo random pattern generators (PRPGs) is provided, each PRPG comprising one or more linear feedback shift registers (LFSRs). Each respective PRPG includes an XOR feedback input selectively receiving a feedback from another PRPG and predefined inputs of the respective PRPG. A respective XOR spreading function is coupled to a plurality of outputs of each PRPG with predefined XOR spreading functions applying test pseudo random pattern inputs to LBIST channels for LBIST diagnostics.
摘要翻译：一种用于实现增强型逻辑内置自检（LBIST）诊断的方法和电路，以及提供主题电路所在的设计结构。提供了多个伪随机模式发生器（PRPG），每个PRPG包括一个或多个线性反馈移位寄存器（LFSR）。每个相应的PRPG包括选择性地接收来自另一PRPG的反馈和相应PRPG的预定义输入的异或反馈输入。相应的XOR扩展功能被耦合到每个PRPG的多个输出，其中预定义的XOR扩展函数将测试伪随机模式输入应用于LBIST通道用于LBIST诊断。

95. 发明授权

US08489858B2 Methods and apparatus for scalable array processor interrupt detection and response 失效
标题翻译：用于可扩展阵列处理器中断检测和响应的方法和装置
公开(公告)号：US08489858B2
公开(公告)日：2013-07-16
申请号：US13417490
申请日：2012-03-12
申请人： Edwin Franklin Barry , Patrick R. Marchand , Gerald George Pechanek , Larry D. Larsen
发明人： Edwin Franklin Barry , Patrick R. Marchand , Gerald George Pechanek , Larry D. Larsen
IPC分类号： G06F15/00
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response are provided in a scalable pipelined array processor environment. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debug monitor mechanism.
摘要翻译：用于中断检测和响应的硬件和软件技术在可扩展的流水线阵列处理器环境中提供。利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。此外，使用分层中断结构，允许使用调试中断的通用调试方法和动态调试监视机制。

96. 发明申请

US20130151901A1 High Volume Recording of Instrumentation Data Varying Instrumentation Volumes to Prevent Data Loss 有权
标题翻译：大容量记录仪表数据不同的仪表卷，以防止数据丢失
公开(公告)号：US20130151901A1
公开(公告)日：2013-06-13
申请号：US12974619
申请日：2010-12-21
申请人： Gary L. Swoboda
发明人： Gary L. Swoboda
IPC分类号： G06F11/27
CPC分类号： G06F11/27 , G06F11/3664
摘要： This invention is an apparatus and method for monitoring an electronic apparatus. At least one capture unit captures data to be monitored. A repeater corresponding to each capture unit repeats the captured data. A first-in-first-out buffer corresponding to each capture unit temporarily stores the captured data. The buffered data supplies a utilization unit. Captured data may be merged after repeating. The capture unit may be in a different voltage domain than the repeater, buffer and utilization unit.
摘要翻译：本发明是用于监视电子设备的装置和方法。至少一个捕获单元捕获要监视的数据。对应于每个捕获单元的中继器重复捕获的数据。对应于每个捕获单元的先进先出缓冲器临时存储捕获的数据。缓冲数据提供一个利用单元。捕获的数据可能会在重复后合并。捕获单元可能处于与中继器，缓冲器和利用单元不同的电压域。

97. 发明申请

US20130114420A1 PHYSICAL LAYER LOOPBACK 有权
标题翻译：物理层回滚
公开(公告)号：US20130114420A1
公开(公告)日：2013-05-09
申请号：US13722942
申请日：2012-12-20
申请人： Theodore Z. Schoenborn , Andrew W. Martwick , David S. Dunning
发明人： Theodore Z. Schoenborn , Andrew W. Martwick , David S. Dunning
IPC分类号： H04L12/26
CPC分类号： G06F11/27 , G01R31/31716 , H04L43/50
摘要： In some embodiments, a chip comprises control circuitry to provide inband signals, inband output ports, and transmitters to transmit the inband signals to the inband output ports. The control circuitry selectively includes loopback initiating commands in the inband signals. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括控制电路，以提供带内信号，带内输出端口和发射器，以将带内信号传输到带内输出端口。控制电路选择性地包括带内信号中的回送启动命令。描述和要求保护其他实施例。

98. 发明申请

US20130019130A1 TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIODICITY 审中-公开
标题翻译：基于故障和测试算法周期测试电子记忆
公开(公告)号：US20130019130A1
公开(公告)日：2013-01-17
申请号：US13183468
申请日：2011-07-15
申请人： Aram HAKHUMYAN , Gurgen Harutyunyan , Samvel Shoukourian , Valery Vardanian , Yervant Zorian
发明人： Aram HAKHUMYAN , Gurgen Harutyunyan , Samvel Shoukourian , Valery Vardanian , Yervant Zorian
IPC分类号： G11C29/12 , G06F11/263 , G06F11/27
CPC分类号： G11C29/18 , G06F11/27 , G11C29/10 , G11C29/16 , G11C29/36 , G11C2029/0405
摘要： Testing electronic memories based on fault and test algorithm periodicity. A processor unit for testing an electronic memory includes a built-in self-test (BIST) finite state machine, an address generator, a data generator, a test algorithm generation unit, a programmable test algorithm register, and a test algorithm register control unit. A memory wrapper unit for testing an electronic memory includes an operation decoder, a data comparator, and an electronic memory under test. The method includes constructing a fault periodic table having columns corresponding with test mechanisms, and rows corresponding with fault families. A first March test sequence and second March test sequence are selected according to respective fault families and test mechanisms, and applied to an electronic memory. The electronic memory under test is determined to be one of acceptable and unacceptable based on results of the first March test sequence and the second March test sequence.
摘要翻译：基于故障和测试算法周期测试电子存储器。用于测试电子存储器的处理器单元包括内置的自检（BIST）有限状态机，地址发生器，数据发生器，测试算法生成单元，可编程测试算法寄存器和测试算法寄存器控制单元。用于测试电子存储器的存储器包装单元包括操作解码器，数据比较器和正在测试的电子存储器。该方法包括构建具有与测试机制相对应的列的故障周期表，以及与故障族对应的行。根据相应的故障族和测试机制选择第一个三月测试序列和第三个三月测试序列，并应用于电子存储器。根据第一个三月份测试序列和三月份测试序列的结果，测试中的电子存储器被确定为可接受的和不可接受的。

99. 发明授权

US08286043B2 System, computer program product and method for testing a logic circuit 有权
标题翻译：用于测试逻辑电路的系统，计算机程序产品和方法
公开(公告)号：US08286043B2
公开(公告)日：2012-10-09
申请号：US12527347
申请日：2007-02-16
申请人： Oleksandr Sakada , Florian Bogenberger
发明人： Oleksandr Sakada , Florian Bogenberger
IPC分类号： G01R31/28 , G01R31/26 , G01R31/02
CPC分类号： G06F11/27 , G01R31/005 , G01R31/007 , G01R31/3183 , G01R31/3187
摘要： A system for testing a logic circuit which has two or more test routine modules. Each module contains a set of instructions which is executable by (a part of) the logic circuit. The set forms a test routine for performing a self-test by the part of the logic circuit. The self-test includes the part of the logic circuit testing itself for faulty behavior, and the part of the logic circuit determining a self-test result of the testing. The system includes a test module which can execute a test application which subjects the logic circuit to a test by performing the self-test on at least a part of the logic circuit by causes the part of the logic circuit to execute a selected test routine, and determining, by the test module, an overall test result at least based on a performed self-tests. The test module includes a control output interface for activates the execution of the a selected test routine. A second test module input interface can receive the self-test result from a selected test routine. At a test module output interface the overall test result may be outputted. The test routine includes instructions for outputting, by the part of the logic circuit, data to a test routine output interface which is not connected to the second test module input interface, for outputting information about the self-test result by the test routines without passing the information through the test module.
摘要翻译：一种用于测试具有两个或更多个测试例程模块的逻辑电路的系统。每个模块包含一组可由逻辑电路的（一部分）执行的指令。该组形成用于由逻辑电路的一部分进行自检的测试程序。自检包括对故障行为进行逻辑电路测试的部分，逻辑电路的一部分决定测试的自检结果。该系统包括测试模块，该测试模块可以通过使逻辑电路的一部分执行所选择的测试例程来执行通过对逻辑电路的至少一部分进行自检来使逻辑电路进行测试的测试应用，以及至少基于所执行的自我测试，由所述测试模块确定总体测试结果。测试模块包括用于激活所选择的测试例程的执行的控制输出接口。第二个测试模块输入接口可以从选定的测试程序中接收自检结果。在测试模块输出接口，可以输出整体测试结果。测试例程包括用逻辑电路的一部分将数据输出到未连接到第二测试模块输入接口的测试程序输出接口，用于通过测试例程输出关于自检结果的信息而不经过通过测试模块的信息。

100. 发明授权

US08284415B2 Image forming apparatus, hardware self-diagnosing method, and hardware self-diagnosing program 有权
标题翻译：图像形成装置，硬件自诊断方法和硬件自诊断程序
公开(公告)号：US08284415B2
公开(公告)日：2012-10-09
申请号：US12390625
申请日：2009-02-23
申请人： Takahiro Yaoyama
发明人： Takahiro Yaoyama
IPC分类号： G06F15/00 , G06F3/12 , G06K1/00 , G06K15/00
CPC分类号： G06K15/00 , G06F11/0733 , G06F11/079 , G06F11/27
摘要： A hardware self-diagnosing method for performing a hardware self-diagnosis of an image forming apparatus includes reading a set value stored in a memory unit of the image forming apparatus; performing the hardware self-diagnosis of the image forming apparatus in a detailed diagnosis mode at intervals determined by the set value stored in the memory unit; and performing the hardware self-diagnosis of the image forming apparatus in a simplified diagnosis mode in between the intervals at which the hardware self-diagnosis is performed in the detailed diagnosis mode. The set value may be a period of time or a number of recording media outputted by the image forming apparatus.
摘要翻译：用于执行图像形成装置的硬件自诊断的硬件自诊断方法包括读取存储在图像形成装置的存储单元中的设定值; 以由存储在存储单元中的设定值确定的间隔以详细诊断模式执行图像形成装置的硬件自诊断; 并且在详细诊断模式中在执行硬件自诊断的间隔之间，以简化诊断模式执行图像形成装置的硬件自诊断。设定值可以是由图像形成装置输出的时间段或记录介质的数量。

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