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91. 发明授权

US08271737B2 Cache auto-flush in a solid state memory device 有权
标题翻译：在固态存储设备中缓存自动刷新
公开(公告)号：US08271737B2
公开(公告)日：2012-09-18
申请号：US12473081
申请日：2009-05-27
申请人： Richard Chen , Rex Hsueh , Ping Hou
发明人： Richard Chen , Rex Hsueh , Ping Hou
IPC分类号： G06F13/00
CPC分类号： G06F12/0804 , G06F12/0866 , G06F2212/214
摘要： A device, system and method in which data in a write cache, that must at some point be written to non-volatile memory, is written to non-volatile memory after expiration of a threshold time period during which no new host commands are received. If either the last dirty entry is written back or a host command is received during the write-back process, the time threshold time period and auto-flush process is restarted.
摘要翻译：在其中没有接收到新的主机命令的阈值时间段期满之后，将写入高速缓存中必须在某点被写入非易失性存储器的数据写入非易失性存储器的设备，系统和方法。如果在回写过程中回写最后一个脏条目或接收到主机命令，则会重新启动时间阈值时间段和自动刷新过程。

92. 发明授权

US08269343B2 Semiconductor device including a pressure-contact section 有权
标题翻译：包括压接部的半导体装置
公开(公告)号：US08269343B2
公开(公告)日：2012-09-18
申请号：US12234337
申请日：2008-09-19
申请人： Kouichi Meguro
发明人： Kouichi Meguro
IPC分类号： H01L23/34
CPC分类号： H01L25/105 , H01L21/568 , H01L23/49551 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/96 , H01L24/97 , H01L2224/05001 , H01L2224/13099 , H01L2224/131 , H01L2224/16237 , H01L2224/16245 , H01L2224/75253 , H01L2224/81001 , H01L2224/81141 , H01L2224/81191 , H01L2224/81224 , H01L2224/81801 , H01L2224/83907 , H01L2224/9202 , H01L2224/97 , H01L2225/1029 , H01L2225/1041 , H01L2225/1064 , H01L2225/1082 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/18161 , H01L2924/3511 , H01L2224/81 , H01L2924/00014
摘要： A semiconductor device in accordance with one embodiment of the invention can include a substrate onto which a wiring pattern is formed. In addition, the semiconductor device can include a plurality of semiconductor packages. Each semiconductor package can include a lead frame that is coupled to an electrode of a semiconductor chip. Each lead frame can be located on a side surface and a bottom surface of the semiconductor package. In addition, the semiconductor device can include a pressure-contact section for receiving the plurality of semiconductor packages and for causing the plurality of semiconductor packages to come into contact with the wiring pattern.
摘要翻译：根据本发明的一个实施例的半导体器件可以包括其上形成有布线图案的基板。此外，半导体器件可以包括多个半导体封装。每个半导体封装可以包括耦合到半导体芯片的电极的引线框架。每个引线框架可以位于半导体封装的侧表面和底表面上。此外，半导体器件可以包括用于接收多个半导体封装件并且使多个半导体封装件与布线图案接触的压接部分。

93. 发明申请

US20120218700A1 ELECTRONIC DEVICES WITH ULTRAVIOLET BLOCKING LAYERS AND PROCESSES OF FORMING THE SAME 有权
标题翻译：具有超紫外线阻挡层的电子器件及其形成方法
公开(公告)号：US20120218700A1
公开(公告)日：2012-08-30
申请号：US13465600
申请日：2012-05-07
申请人： Bryon K. Hance , Brian D. White , William Brennan , Joseph W. Wiseman , Allen Evans
发明人： Bryon K. Hance , Brian D. White , William Brennan , Joseph W. Wiseman , Allen Evans
IPC分类号： G06F1/16 , H05K1/00 , H05K1/18
CPC分类号： H01L21/76802 , H01L21/76807 , H01L21/76829 , H01L21/76834
摘要： An electronic device can include a conductive feature and an ultraviolet (“UV”) blocking layer overlying the conductive feature. The electronic device can also include an insulating layer overlying the UV blocking layer. The electronic device can further include a conductive structure extending into an opening within the insulating layer, wherein the conductive structure is electrically connected to the conductive feature. In one aspect, the UV blocking layer lies within 90 nm of the conductive structure. The insulating layer can be at least 4 times thicker than the UV blocking layer. In another aspect, a method can be used in forming the electronic device. In still a further aspect, a system can include the electronic device, a processor, and a display, wherein the processor is electrically coupled to the electronic device and the display.
摘要翻译：电子设备可以包括导电特征和覆盖导电特征的紫外线（“UV”）阻挡层。电子器件还可以包括覆盖在UV阻挡层上的绝缘层。电子设备还可以包括延伸到绝缘层内的开口中的导电结构，其中导电结构电连接到导电特征。在一个方面，UV阻挡层位于导电结构的90nm内。绝缘层可以是至少比UV阻挡层厚4倍。另一方面，一种方法可用于形成电子设备。在另一方面，系统可以包括电子设备，处理器和显示器，其中处理器电耦合到电子设备和显示器。

94. 发明授权

US08244964B2 Read preamble for data capture optimization 有权
标题翻译：读取前导码用于数据捕获优化
公开(公告)号：US08244964B2
公开(公告)日：2012-08-14
申请号：US12646279
申请日：2009-12-23
申请人： Clifford Alan Zitlaw
发明人： Clifford Alan Zitlaw
IPC分类号： G06F12/00 , H04L12/56
CPC分类号： G11C16/32 , G11C16/26 , G11C2216/30
摘要： Systems and/or methods are provided that facilitate data capture optimization for devices accessing memories via a bus. In an aspect, a memory can output a read preamble prior to pushing data onto a bus. The read preamble can be a known sequence of one or more bits. A host device accessing the memory via the bus can analyze the read preamble and, particularly, timing characteristics of the read preamble. The timing characteristics can be utilized to identify an optimal capture point within a window of data validity.
摘要翻译：提供了用于经由总线访问存储器的设备的数据捕获优化的系统和/或方法。在一方面，存储器可以在将数据推送到总线之前输出读取前同步码。读取的前同步码可以是一个或多个比特的已知序列。通过总线访问存储器的主机设备可以分析读取前置码，特别是读取前置码的定时特性。时序特征可用于识别数据有效性窗口内的最佳捕获点。

95. 发明申请

US20120202355A1 PATTERNED DUMMY WAFERS LOADING IN BATCH TYPE CVD 有权
标题翻译：刻板式CVD中加载的图案式加湿器
公开(公告)号：US20120202355A1
公开(公告)日：2012-08-09
申请号：US13022517
申请日：2011-02-07
申请人： Rinji Sugino , Bradley Marc Davis , Lei Xue , Kenichi Ohtsuka
发明人： Rinji Sugino , Bradley Marc Davis , Lei Xue , Kenichi Ohtsuka
IPC分类号： H01L21/465 , H01L21/46
CPC分类号： H01L21/02271 , C23C16/045 , C23C16/44 , C23C16/56 , H01L21/02164 , H01L27/11568
摘要： A method for semiconductor device fabrication is provided. Embodiments of the present invention are directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. In another embodiment, at least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes.
摘要翻译：提供了半导体器件制造方法。本发明的实施例涉及在膜沉积系统中使用至少一个图案化虚设晶圆以及一个或多个产品晶片，以产生在所有产品晶片上基本均匀的侧壁层厚度变化。至少一个图案化的虚设晶片可以具有高密度图案化的衬底表面，其具有不同于或基本类似于一个或多个产品晶片的形貌的形貌。此外，在间歇式化学气相沉积（CVD）系统中，至少一个图案化的虚设晶片可以放置在CVD系统的气体入口附近。在另一个实施例中，至少一个图案化虚设晶片可以放置在CVD系统的排气附近。此外，图案化的虚拟晶片可以在随后的成膜工艺中可重复使用。

96. 发明授权

US08232515B2 Imaging device having a radiation detecting structure disposed at a semiconductor substrate with a thermalizing material and a first radiation-reactive material sensitive to neutron radiation 有权
标题翻译：具有放射线检测结构的成像装置，其设置在具有热化材料的半导体衬底和对中子辐射敏感的第一辐射反应性材料
公开(公告)号：US08232515B2
公开(公告)日：2012-07-31
申请号：US12472735
申请日：2009-05-27
申请人： Timothy Z. Hossain , Patrick Mark Clopton , Clayton Fullwood , Dan E. Posey
发明人： Timothy Z. Hossain , Patrick Mark Clopton , Clayton Fullwood , Dan E. Posey
IPC分类号： H01L31/00
CPC分类号： H01L27/14676 , H01L27/14609 , H01L27/1462
摘要： An imaging device suitable for detecting certain imaging particles and recording the detection of imaging particles, and as such can include certain recording devices such as a charge storage structure.
摘要翻译：适合于检测某些成像粒子并记录成像粒子的检测的成像装置，因此可以包括某些记录装置，例如电荷存储结构。

97. 发明授权

US08232209B2 Processes for forming electronic devices including polishing metal-containing layers 有权
标题翻译：用于形成包括抛光含金属层的电子器件的方法
公开(公告)号：US08232209B2
公开(公告)日：2012-07-31
申请号：US13025979
申请日：2011-02-11
申请人： Christopher E. Brannon , Michael Wedlake , Chris A. Nauert
发明人： Christopher E. Brannon , Michael Wedlake , Chris A. Nauert
IPC分类号： H01L21/302
CPC分类号： B24B37/042 , B24B49/16 , H01L21/3212 , H01L21/7684
摘要： A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed.
摘要翻译：形成电子设备的过程可以包括提供工件。工件可以包括衬底，覆盖衬底的层间电介质，层间电介质上的含难熔金属的层，以及位于难熔金属含有层上的第一含金属层。第一含金属层可以包括不同于难熔金属元素的金属元素。该方法还包括将第一含金属层和含难熔金属层作为连续作用进行抛光以暴露层间电介质。在一个实施例中，金属元件可以包括铜，镍或贵金属。在另一个实施方案中，可以使用选择剂进行抛光以减少去除的层间电介质的量。

98. 发明授权

US08209463B2 Expansion slots for flash memory based random access memory subsystem 有权
标题翻译：用于基于闪存的随机存取存储器子系统的扩展槽
公开(公告)号：US08209463B2
公开(公告)日：2012-06-26
申请号：US12026296
申请日：2008-02-05
申请人： Tzungren Allan Tzeng
发明人： Tzungren Allan Tzeng
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7203 , G06F2212/7211
摘要： A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.
摘要翻译：提供了一种存储系统。该系统包括控制器，其调节对用于随机存取存储器应用的一个或多个闪速存储器设备的读取和写入访问。缓冲器组件与控制器一起操作以调节对一个或多个FLASH设备的读取和写入访问。提供磨损均衡部件以及读取和写入处理部件以便于闪速存储器件的有效操作。

99. 发明授权

US08183622B2 Flash memory device comprising bit-line contact region with dummy layer between adjacent contact holes 有权
标题翻译：闪存器件包括在相邻的接触孔之间具有虚设层的位线接触区域
公开(公告)号：US08183622B2
公开(公告)日：2012-05-22
申请号：US11495116
申请日：2006-07-27
申请人： Masatomi Okanishi
发明人： Masatomi Okanishi
IPC分类号： H01L27/115 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115
摘要： A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width direction of the bit lines (12); and a dummy layer (44) that extends in the width direction of the bit lines (12) and is provided in a bit-line contact region (40) having contact holes formed to connect the bit lines (12) with wiring layers (34). In accordance with the present invention, the proximity effect at the time of word line formation can be restrained, and the variation in the widths of the word lines can be made smaller, or current leakage between the bit lines and the semiconductor substrate can be restrained.
摘要翻译：半导体器件包括设置在半导体衬底（10）中的设置在半导体衬底上的ONO膜（14）的位线（12）设置在ONO膜（14）上并在位线（12）的宽度方向上延伸的字线; 以及在位线（12）的宽度方向上延伸并设置在具有形成为将位线（12）与布线层（34）连接的接触孔的位线接触区域（40）中的虚设层（44））。根据本发明，可以抑制字线形成时的邻近效应，并且可以使字线宽度的变化更小，或者可以抑制位线和半导体衬底之间的电流泄漏。

100. 发明授权

US08148771B2 Semiconductor device and method to manufacture thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08148771B2
公开(公告)日：2012-04-03
申请号：US12837323
申请日：2010-07-15
申请人： Masataka Hoshino , Ryoto Fukuyama , Koji Taya
发明人： Masataka Hoshino , Ryoto Fukuyama , Koji Taya
IPC分类号： H01L21/02
CPC分类号： H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2221/6834 , H01L2221/68359 , H01L2224/13009 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/16237 , H01L2224/29111 , H01L2224/2919 , H01L2224/81193 , H01L2224/81801 , H01L2224/83102 , H01L2224/92125 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01077 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/00014
摘要： A semiconductor device 100 includes a semiconductor substrate 14, a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which penetrates the semiconductor substrate 14 and the connection electrode 20, and an insulation portion 30 interposed between the semiconductor substrate 14 and the through electrode 20. The through electrode 20 is integrally formed to protrude outward from upper surfaces of the semiconductor substrate 14 and the connection electrode 12, and connected to the connection electrode 12 in a region where the through electrode 20 penetrates the connection electrode 12.
摘要翻译：半导体器件100包括半导体衬底14，连接电极12，其设置在半导体衬底14的上表面上并连接到其上的集成电路，贯穿半导体衬底14和连接电极20的贯通电极20和绝缘部分30插入在半导体衬底14和贯通电极20之间。贯通电极20一体地形成为从半导体衬底14和连接电极12的上表面向外突出，并连接到连接电极12，通孔电极20穿透连接电极12。

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