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1. 发明申请

US20120317348A1 MITIGATE FLASH WRITE LATENCY AND BANDWIDTH LIMITATION 失效
标题翻译：缓解闪存写入延迟和带宽限制
公开(公告)号：US20120317348A1
公开(公告)日：2012-12-13
申请号：US13590294
申请日：2012-08-21
申请人： Tzungren Allan Tzeng
发明人： Tzungren Allan Tzeng
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7203 , G06F2212/7211
摘要： A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.
摘要翻译：提供了一种操作存储器系统的方法。该方法包括控制器，其调节对用于随机存取存储器应用的一个或多个闪速存储器设备的读取和写入访问。缓冲器组件与控制器一起操作以调节对一个或多个FLASH设备的读取和写入访问。提供磨损均衡部件以及读取和写入处理部件以便于闪速存储器件的有效操作。

2. 发明授权

US08332572B2 Wear leveling mechanism using a DRAM buffer 有权
标题翻译：使用DRAM缓冲器的磨损均衡机制
公开(公告)号：US08332572B2
公开(公告)日：2012-12-11
申请号：US12026299
申请日：2008-02-05
申请人： Tzungren Allan Tzeng
发明人： Tzungren Allan Tzeng
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7203 , G06F2212/7211 , Y02D10/13
摘要： A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.
摘要翻译：提供了一种存储系统。该系统包括控制器，其调节对用于随机存取存储器应用的一个或多个闪速存储器设备的读取和写入访问。缓冲器组件与控制器一起操作以调节对一个或多个FLASH设备的读取和写入访问。提供磨损均衡部件以及读取和写入处理部件以便于闪速存储器件的有效操作。

3. 发明申请

US20090248957A1 MEMORY RESOURCE MANAGEMENT FOR A FLASH AWARE KERNEL 有权
标题翻译：闪存卡的记忆资源管理
公开(公告)号：US20090248957A1
公开(公告)日：2009-10-01
申请号：US12059795
申请日：2008-03-31
申请人： Tzungren Allan Tzeng
发明人： Tzungren Allan Tzeng
IPC分类号： G06F12/02
CPC分类号： G06F13/4239
摘要： A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.
摘要翻译：提供了一种存储系统。该系统包括操作系统内核，其调节对用于随机存取存储器应用的一个或多个闪速存储器设备的读取和写入访问。缓冲器组件与内核一起操作以调节对一个或多个FLASH设备的读取和写入访问。

4. 发明申请

US20090225915A1 SKEW TOLERANT COMMUNICATION BETWEEN RATIOED SYNCHRONOUS CLOCKS 有权
标题翻译：比较同步时钟之间的容忍通信
公开(公告)号：US20090225915A1
公开(公告)日：2009-09-10
申请号：US12043935
申请日：2008-03-06
申请人： Mahmudul Hassan , Tzungren Allan Tzeng
发明人： Mahmudul Hassan , Tzungren Allan Tzeng
IPC分类号： H04L7/00
CPC分类号： H04L7/0012 , G06F5/06
摘要： A data communications system is disclosed. The data communications system comprises two clock domains. Each of the clock domains are coupled to receive a source clock signal. The first clock domain includes a first clock signal and the second clock domain includes a second clock signal, each of the first clock signal and the second clock signal are derived from the source clock signal. The first clock signal has a frequency which is different from that of the second clock signal. The system includes circuitry configured to generate a pulse indicative of when data transferred between the first clock domain and the second clock domain may be latched. Data is only latched when the pulse is asserted and on a given edge of the first clock signal, and the circuitry is configured to generate the pulse such that the given edge occurs at approximately a position corresponding to a middle of a period of the second clock signal.
摘要翻译：公开了一种数据通信系统。数据通信系统包括两个时钟域。每个时钟域被耦合以接收源时钟信号。第一时钟域包括第一时钟信号，并且第二时钟域包括第二时钟信号，第一时钟信号和第二时钟信号中的每个从源时钟信号导出。第一时钟信号具有与第二时钟信号不同的频率。该系统包括被配置为产生指示何时可以锁存在第一时钟域和第二时钟域之间传送的数据的脉冲的电路。当脉冲被置位并且在第一时钟信号的给定边缘上时，数据被锁存，并且电路被配置为产生脉冲，使得给定边缘出现在对应于第二时钟周期的中间的大致位置信号。

5. 发明授权

US06751644B1 Method and apparatus for elimination of inherent carries 有权
标题翻译：用于消除固有载体的方法和装置
公开(公告)号：US06751644B1
公开(公告)日：2004-06-15
申请号：US09542748
申请日：2000-04-04
申请人： Choon-Ping Chng , Tzungren Allan Tzeng
发明人： Choon-Ping Chng , Tzungren Allan Tzeng
IPC分类号： G06F738
CPC分类号： G06F7/5324 , G06F7/4876 , G06F7/49994 , G06F7/5338
摘要： A fused instruction datapath is disclosed. The fused instruction datapath may include a normalization unit, a floating point mutltiplier coupled to the normalization unit, and a mantissa alignment unit coupled to provide an aligned mantissa to the floating point multiplier. The floating point multiplier may include a term generation unit and a compensation unit coupled to the term generation unit. The term generation unit may be configured to generate a sum term and a carry term. The compensation unit may be configured to compensate the sum term.
摘要翻译：公开了融合指令数据通路。融合指令数据通路可以包括归一化单元，耦合到归一化单元的浮点互补器和耦合以向浮点乘法器提供对齐尾数的尾数对齐单元。浮点乘法器可以包括术语生成单元和耦合到术语生成单元的补偿单元。术语生成单元可以被配置为生成和项和进位项。补偿单元可以被配置为补偿和项。

6. 发明授权

US08458393B2 Flash memory and operating system kernel 有权
标题翻译：闪存和操作系统内核
公开(公告)号：US08458393B2
公开(公告)日：2013-06-04
申请号：US12059816
申请日：2008-03-31
申请人： Tzungren Allan Tzeng
发明人： Tzungren Allan Tzeng
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/08 , G06F2212/2022 , G06F2212/205
摘要： A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.
摘要翻译：提供了一种存储系统。该系统包括操作系统内核，其调节对用于随机存取存储器应用的一个或多个闪速存储器设备的读取和写入访问。缓冲器组件与内核一起操作以调节对一个或多个FLASH设备的读取和写入访问。

7. 发明授权

US06647404B2 Double precision floating point multiplier having a 32-bit booth-encoded array multiplier 有权
公开(公告)号：US06647404B2
公开(公告)日：2003-11-11
申请号：US10217740
申请日：2002-08-12
申请人： Tzungren Allan Tzeng , Choon Ping Chng
发明人： Tzungren Allan Tzeng , Choon Ping Chng
IPC分类号： G06F752
CPC分类号： G06F7/5324 , G06F7/4876 , G06F7/49994 , G06F7/5338
摘要： A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and summing these in the carry-save partial-product accumulator. The partial-product accumulator has a carry-save adder, a sum register, a carry-out counter and an extender. The carry-out counter receives a carry outputs of the carry-save adder and array multiplier, and the extender is coupled to extend the sum register dependent upon the contents of the carry-out counter. The extension occurs during addition of the most significant partial product to the sum of less significant partial products.

8. 发明授权

US06446104B1 Double precision floating point multiplier having a 32-bit booth-encoded array multiplier 有权
标题翻译：双精度浮点乘数，具有32位展位编码阵列乘数
公开(公告)号：US06446104B1
公开(公告)日：2002-09-03
申请号：US09396236
申请日：1999-09-15
申请人： Tzungren Allan Tzeng , Choon Ping Chng
发明人： Tzungren Allan Tzeng , Choon Ping Chng
IPC分类号： G06F744
CPC分类号： G06F7/5324 , G06F7/4876 , G06F7/49994 , G06F7/5338
摘要： A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and summing these in the carry-save partial-product accumulator. The partial-product accumulator has a carry-save adder, a sum register, a carry-out counter and an extender. The carry-out counter receives a carry outputs of the carry-save adder and array multiplier, and the extender is coupled to extend the sum register dependent upon the contents of the carry-out counter. The extension occurs during addition of the most significant partial product to the sum of less significant partial products.
摘要翻译：用于处理器的浮点流水线的双精度乘法器具有阵列乘法器和进位保存部分乘积累加器。通过生成多个部分乘积并在进位保存部分乘积累加器中求和这些来实现双精度乘法。部分积累器具有进位保存加法器，和寄存器，进位计数器和扩展器。进位计数器接收进位存储加法器和阵列乘法器的进位输出，并且扩展器被耦合以根据执行计数器的内容来扩展和寄存器。在将最重要的部分产品添加到不太重要的部分产品的总和中时，延伸发生。

9. 发明授权

US08745311B2 Flash memory usability enhancements in main memory application 失效
标题翻译：主内存应用程序中的闪存可用性增强
公开(公告)号：US08745311B2
公开(公告)日：2014-06-03
申请号：US12059809
申请日：2008-03-31
申请人： Tzungren Allan Tzeng
发明人： Tzungren Allan Tzeng
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/08 , G06F2212/2022 , G06F2212/205
摘要： A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.
摘要翻译：提供了一种存储系统。该系统包括操作系统内核，其调节对用于随机存取存储器应用的一个或多个闪速存储器设备的读取和写入访问。缓冲器组件与内核一起操作以调节对一个或多个FLASH设备的读取和写入访问。

10. 发明授权

US08738840B2 Operating system based DRAM/FLASH management scheme 有权
标题翻译：基于操作系统的DRAM / FLASH管理方案
公开(公告)号：US08738840B2
公开(公告)日：2014-05-27
申请号：US12059784
申请日：2008-03-31
申请人： Tzungren Allan Tzeng
发明人： Tzungren Allan Tzeng
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/214 , G06F2212/7201
摘要： A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.
摘要翻译：提供了一种存储系统。该系统包括操作系统内核，其控制对用于随机存取存储器应用的一个或多个闪速存储器设备的读取和写入访问。缓冲器组件与内核一起操作以调节对一个或多个FLASH设备的读取和写入访问。

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