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91. 发明授权

US07347900B2 Chemical vapor deposition apparatus and method 失效
标题翻译：化学气相沉积装置及方法
公开(公告)号：US07347900B2
公开(公告)日：2008-03-25
申请号：US10735912
申请日：2003-12-16
申请人： Seung-Chul Choi
发明人： Seung-Chul Choi
IPC分类号： C23C16/52 , C23C16/455 , C23C16/458 , C23C16/00 , G06F19/00 , H01L21/3065
CPC分类号： C23C16/45565 , C23C16/455 , C23C16/4583
摘要： A chemical vapor deposition (CVD) apparatus includes a process chamber where a deposition process is performed on a wafer. A gas supply assembly is mounted in the process chamber for supplying a process gas to the process chamber, and a vacuum pump is mounted in the process chamber for exhausting the process gas. A support is mounted in the process chamber for supporting the wafer, and a position control assembly raises and lowers the chuck. A controller controls the position control assembly to vary a distance between the wafer and the gas supply assembly during the deposition process. A CVD method for forming a deposition layer on a wafer includes supplying a process gas to a process chamber, dividing a process time into a plurality of process stages, varying a distance between the wafer and a gas supply assembly according to the process stages, and exhausting the process gas.
摘要翻译：化学气相沉积（CVD）装置包括在晶片上进行沉积处理的处理室。气体供应组件安装在处理室中，用于向处理室供应处理气体，并且真空泵安装在处理室中以排出处理气体。支撑件安装在处理室中用于支撑晶片，位置控制组件升高并降低卡盘。在沉积过程中，控制器控制位置控制组件以改变晶片和气体供应组件之间的距离。用于在晶片上形成沉积层的CVD方法包括：将处理气体供应到处理室，将处理时间分为多个处理阶段，根据处理阶段改变晶片和气体供应组件之间的距离;以及排出工艺气体。

92. 发明申请

US20080067582A1 Semiconductor device and method of manufacturing the semiconductor device 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080067582A1
公开(公告)日：2008-03-20
申请号：US11984012
申请日：2007-11-13
申请人： Tae-Hong Lim
发明人： Tae-Hong Lim
IPC分类号： H01L29/78
CPC分类号： H01L29/66553 , H01L21/823437 , H01L21/823462 , H01L21/823487 , H01L29/66787
摘要： A semiconductor device includes a pair of first source/drain regions disposed on a silicon substrate. A first silicon epitaxial layer pattern defines a gate forming region that exposes the silicon substrate between the pair of first source/drain regions. A first gate insulation layer is disposed on the silicon substrate in the gate forming region. A second gate insulation layer is disposed on a sidewall of the first silicon epitaxial layer pattern. A second silicon epitaxial layer pattern is disposed in the gate forming region and on the first silicon epitaxial layer pattern. A pair of second source/drain regions is disposed on the second silicon epitaxial layer pattern. A third gate insulation layer exposes the second silicon epitaxial layer pattern in the gate forming region and covers the pair of second source/drain regions. A gate is disposed on the second silicon epitaxial layer pattern in the gate forming region.
摘要翻译：半导体器件包括设置在硅衬底上的一对第一源极/漏极区域。第一硅外延层图案限定了在一对第一源极/漏极区域之间暴露硅衬底的栅极形成区域。第一栅极绝缘层设置在栅极形成区域中的硅衬底上。第二栅极绝缘层设置在第一硅外延层图案的侧壁上。在栅极形成区域和第一硅外延层图案上设置第二硅外延层图案。一对第二源极/漏极区域设置在第二硅外延层图案上。第三栅极绝缘层在栅极形成区域中暴露第二硅外延层图案并覆盖该对第二源极/漏极区域。在栅极形成区域中的第二硅外延层图案上设置栅极。

93. 发明授权

US07338870B2 Methods of fabricating semiconductor devices 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07338870B2
公开(公告)日：2008-03-04
申请号：US11026714
申请日：2004-12-30
申请人： Hyun Soo Shin
发明人： Hyun Soo Shin
IPC分类号： H01L21/336
CPC分类号： H01L21/3003 , H01L21/823481 , H01L29/66575
摘要： Methods of recovering damage on a semiconductor device by performing a hydrogen annealing process are disclosed. An example disclosed method includes forming an STI structure on a semiconductor substrate; forming a gate electrode and spacers on the sidewalls of the gate electrode; implanting ions into source and drain regions and performing a hydrogen annealing process; and performing a thermal treatment for the resulting structure to diffuse and align the ions in the source/drain region.
摘要翻译：公开了通过进行氢退火处理在半导体器件上恢复损伤的方法。所揭示的方法包括在半导体衬底上形成STI结构; 在栅电极的侧壁上形成栅电极和间隔物; 将离子注入源区和漏区并进行氢退火处理; 并且对所得结构进行热处理以使源/漏区中的离子扩散和对准。

94. 发明授权

US07335585B2 Method for preventing the formation of a void in a bottom anti-reflective coating filling a via hole 失效
标题翻译：防止在填充通孔的底部防反射涂层中形成空隙的方法
公开(公告)号：US07335585B2
公开(公告)日：2008-02-26
申请号：US10969550
申请日：2004-10-20
申请人： Yong Jun Choi
发明人： Yong Jun Choi
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , Y10S430/108
摘要： A method for manufacturing a semiconductor device which, on performing a via first Dual Damascene process, inhibits or prevents the formation of a void in a bottom anti-reflective coating filling a via hole. The method typically includes the steps of forming a bottom anti-reflective coating (BARC) in a via hole in an interlayer dielectric on a semiconductor substrate sufficiently to fill the via hole; disposing an acid diffusion material on the BARC; forming a cross-link layer between the BARC and the acid diffusion material; removing the remaining acid diffusion material; and etching the cross-link layer, the BARC and the interlayer dielectric to form a trench extending from an upper portion of the via hole.
摘要翻译：一种用于制造半导体器件的方法，所述半导体器件在执行通孔第一双镶嵌工艺时，抑制或防止在填充通孔的底部抗反射涂层中形成空隙。该方法通常包括以下步骤：在半导体衬底上的层间电介质的通孔中形成底部抗反射涂层（BARC），以充分填充通孔; 在BARC上设置酸扩散材料; 在BARC和酸扩散材料之间形成交联层; 除去剩余的酸扩散材料; 并且蚀刻交联层，BARC和层间电介质以形成从通孔的上部延伸的沟槽。

95. 发明授权

US07316958B2 Masks for fabricating semiconductor devices and methods of forming mask patterns 失效
标题翻译：用于制造半导体器件的掩模和形成掩模图案的方法
公开(公告)号：US07316958B2
公开(公告)日：2008-01-08
申请号：US11022612
申请日：2004-12-27
申请人： Jun Seok Lee
发明人： Jun Seok Lee
IPC分类号： H01L21/336
CPC分类号： G03F1/29 , H01L21/823892 , Y10S438/949
摘要： Masks for fabricating a semiconductor device and methods of forming mask patterns are provided which are capable of enhancing the breakdown voltage of the fabricated semiconductor device by accurately correcting a line width pattern error of a semiconductor substrate due to a mask error during a process for forming a well ion implantation mask pattern. A disclosed mask used to manufacture a semiconductor device having complementary N-well and P-well includes: a master mask for the complementary N-well and P-well; and a light-blocking pattern on the master mask, wherein a region of the master mask, which is not a portion of the master mask adjacent to the light-blocking pattern, is etched by a predetermined thickness to have a phase shifting function.
摘要翻译：提供了用于制造半导体器件的掩模和形成掩模图案的方法，其能够通过在形成半导体器件的工艺期间由于掩模误差精确校正半导体衬底的线宽图案误差而增强制造的半导体器件的击穿电压良好的离子注入掩模图案。用于制造具有互补N阱和P阱的半导体器件的公开掩模包括：用于互补N阱和P阱的主掩模; 以及主掩模上的遮光图案，其中不是与遮光图案相邻的主掩模的一部分的主掩模的区域被蚀刻预定厚度以具有相移功能。

96. 发明授权

US07315174B2 Method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device 失效
标题翻译：测量MOS晶体管器件中栅极氧化物的平带状态电容的方法
公开(公告)号：US07315174B2
公开(公告)日：2008-01-01
申请号：US11646515
申请日：2006-12-28
申请人： Chang Soo Jang
发明人： Chang Soo Jang
IPC分类号： G01R27/26 , G01R31/26 , G01B7/02
CPC分类号： G01R31/2621 , G01R27/2605 , H01L22/14
摘要： A method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device is disclosed. According to the method of measuring flat-band status capacitance of gate oxide in MOS transistor device, flat-band status capacitance of gate oxide in MOS transistor device can be automatically measured and immediately analyzed by using a characteristics measuring system that changes in accordance with a gate voltage.
摘要翻译：公开了一种测量MOS晶体管器件中的栅极氧化物的平带状态电容的方法。根据测量MOS晶体管器件中栅极氧化物的平带状态电容的方法，MOS晶体管器件中栅极氧化物的平带状态电容可以被自动测量并立即通过使用根据栅极电压。

97. 发明授权

US07312147B2 Method of forming barrier metal in semiconductor device 失效
标题翻译：在半导体器件中形成阻挡金属的方法
公开(公告)号：US07312147B2
公开(公告)日：2007-12-25
申请号：US11024795
申请日：2004-12-30
申请人： Jae Won Han
发明人： Jae Won Han
IPC分类号： H01L21/4763
CPC分类号： H01L21/76807 , H01L21/76844
摘要： A method of forming a barrier metal in a semiconductor device. The present invention includes forming an insulating layer on a substrate having a lower metal line formed thereon, forming an opening exposing the lower metal line through the insulating layer, and forming a barrier metal layer on a sidewall of the opening and the insulating layer except the lower metal line by applying a positive voltage to the substrate.
摘要翻译：在半导体器件中形成阻挡金属的方法。本发明包括在其上形成有下金属线的基板上形成绝缘层，形成通过绝缘层暴露下金属线的开口，并且在开口和绝缘层的侧壁上形成阻挡金属层，除了通过向衬底施加正电压来降低金属线。

98. 发明授权

US07312116B2 Method for forming a MIM capacitor in a semiconductor device 失效
标题翻译：在半导体器件中形成MIM电容器的方法
公开(公告)号：US07312116B2
公开(公告)日：2007-12-25
申请号：US11316631
申请日：2005-12-20
申请人： Joo-Hyun Lee
发明人： Joo-Hyun Lee
IPC分类号： H01L21/8242
CPC分类号： H01L28/60 , H01L21/76823 , H01L21/76825
摘要： In a method of forming a metal-insulator-metal (MIM) capacitor in a semiconductor device, after forming a capacitor insulation layer on a lower metal layer of the MIM capacitor, an upper electrode is formed by ion implantation into the capacitor insulation layer and silicidation, without a typical reactive ion etching process. Consequently, damage to the capacitor insulation layer can be minimized, and the area of the capacitor need not increase.
摘要翻译：在半导体装置中形成金属 - 绝缘体 - 金属（MIM）电容器的方法中，在MIM电容器的下部金属层上形成电容器绝缘层之后，通过离子注入形成上部电极到电容器绝缘层，硅化，没有典型的反应离子蚀刻工艺。因此，电容器绝缘层的损坏可以最小化，并且电容器的面积不必增加。

99. 发明授权

US07307017B2 Semiconductor devices and fabrication methods thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07307017B2
公开(公告)日：2007-12-11
申请号：US10852823
申请日：2004-05-25
申请人： Han-Choon Lee , Jin-Woo Park
发明人： Han-Choon Lee , Jin-Woo Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/28052 , H01L21/28518 , H01L21/321 , H01L29/665
摘要： Semiconductor devices and methods of fabricating semiconductor devices are disclosed. A disclosed semiconductor device includes a silicon substrate, a source region and a drain region. A gate electrode is formed on the silicon substrate. Also, a metal silicide layer is formed on each of the gate electrode, the source region, and the drain region. The metal silicide layer has a thickness uniformity of about 1˜20%. A disclosed fabrication method includes forming a metal layer on a silicon substrate having a gate electrode, a source region, and a drain region; performing a plasma treatment on the metal layer; forming a protective layer on the metal layer; and heat treating the silicon substrate on which the protective layer is formed to thereby form a metal silicide layer. A gas that includes nitrogen is used as a plasma gas during the plasma treatment.
摘要翻译：公开了制造半导体器件的半导体器件和方法。所公开的半导体器件包括硅衬底，源极区和漏极区。在硅衬底上形成栅电极。而且，在栅极电极，源极区域和漏极区域中的每一个上形成金属硅化物层。金属硅化物层的厚度均匀度为约1〜20％。所公开的制造方法包括在具有栅电极，源极区和漏极区的硅衬底上形成金属层; 对金属层进行等离子体处理; 在金属层上形成保护层; 对其上形成保护层的硅衬底进行热处理从而形成金属硅化物层。在等离子体处理期间，使用包含氮气的气体作为等离子体气体。

100. 发明授权

US07307015B2 Method for forming an interconnection line in a semiconductor device 失效
标题翻译：在半导体器件中形成互连线的方法
公开(公告)号：US07307015B2
公开(公告)日：2007-12-11
申请号：US11181275
申请日：2005-07-13
申请人： Date-Gun Lee
发明人： Date-Gun Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L2221/1031
摘要： The CD uniformity of a damascene pattern and the reliability of interconnection lines may be enhanced when a semiconductor device is manufactured by a method including: forming a first insulating layer on a semiconductor substrate, the first insulating layer having a contact hole partially exposing the substrate; forming a photoresist layer filling the contact hole; removing the photoresist layer such that the first insulating layer is exposed and a recess is formed in the contact hole; reducing, removing or substantially eliminating the recess by removing an upper portion of the first insulating layer; forming a second insulating layer having a trench exposing the photoresist layer and a portion of the first insulating layer adjacent thereto; and removing the remaining photoresist layer.
摘要翻译：当半导体器件通过以下方法制造半导体器件时，可以增强镶嵌图案的CD均匀性和互连线的可靠性：包括：在半导体衬底上形成第一绝缘层，第一绝缘层具有部分地暴露衬底的接触孔; 形成填充所述接触孔的光致抗蚀剂层; 去除光致抗蚀剂层，使得第一绝缘层暴露并且在接触孔中形成凹部; 通过去除第一绝缘层的上部来减少，去除或基本上消除凹部; 形成具有暴露光致抗蚀剂层的沟槽和与其相邻的第一绝缘层的一部分的第二绝缘层; 并除去剩余的光致抗蚀剂层。

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