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1. 发明申请

US20150140133A1 IN SITU CONTROLLED RELEASE DRUG DELIVERY SYSTEM 审中-公开
标题翻译：在现场控制释放药物递送系统
公开(公告)号：US20150140133A1
公开(公告)日：2015-05-21
申请号：US14560029
申请日：2014-12-04
申请人： Tae-Hong Lim
发明人： Tae-Hong Lim
IPC分类号： A61K47/34 , A61K47/36 , A61K31/445 , A61K31/44 , A61K31/485 , A61K31/439 , A61K31/137 , A61K31/55 , A61K31/4741 , A61K36/66 , A61K31/606 , A61K31/655 , A61K31/60 , A61K31/192 , A61K45/06 , A61K9/00 , A61K9/06
CPC分类号： A61K47/34 , A61K9/0019 , A61K9/0024 , A61K9/06 , A61K9/1647 , A61K9/5031 , A61K9/5084 , A61K31/137 , A61K31/192 , A61K31/439 , A61K31/44 , A61K31/445 , A61K31/4741 , A61K31/485 , A61K31/55 , A61K31/60 , A61K31/606 , A61K31/655 , A61K36/66 , A61K45/06 , A61K47/36
摘要： A system is described for long-term controlled release delivery of a drug or a therapeutic agent. According to the invention, one or more drugs or therapeutic agents contained in microspheres are mixed with a temperature sensitive hydrogel which is then introduced directly to the desired situs of the drug or therapeutic agent. The temperature sensitive hydrogel may also contain a drug or a therapeutic agent, for example, a pain relieving drug, for a short-term controlled release. The temperature sensitive hydrogel is in liquid state at room temperature, but upon injection, shortly becomes gelatinous. This system is particularly suitable for treatment of diseases, disorders, or conditions, for example, tumors, discogenic back pain, or arthritis, warranting localized administration of a drug or a therapeutic agent. In addition, the specification provides a method for production of a drug- or therapeutic agent-containing microspheres.
摘要翻译：描述了用于药物或治疗剂的长期控制释放递送的系统。根据本发明，将微球中包含的一种或多种药物或治疗剂与温度敏感的水凝胶混合，然后将其直接引入药物或治疗剂的所需位置。对于短期控释，温敏水凝胶也可含有药物或治疗剂，例如止痛药。温度敏感的水凝胶在室温下处于液态，但注射后不久便变成凝胶状。该系统特别适用于治疗疾病，病症或病症，例如肿瘤，椎间盘背痛或关节炎，需要局部施用药物或治疗剂。此外，本说明书提供了制备含药物或治疗剂的微球体的方法。

2. 发明授权

US07714380B2 Semiconductor device and method of manufacturing the semiconductor device 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07714380B2
公开(公告)日：2010-05-11
申请号：US11984012
申请日：2007-11-13
申请人： Tae-Hong Lim
发明人： Tae-Hong Lim
IPC分类号： H01L29/78
CPC分类号： H01L29/66553 , H01L21/823437 , H01L21/823462 , H01L21/823487 , H01L29/66787
摘要： A semiconductor device includes a pair of first source/drain regions disposed on a silicon substrate. A first silicon epitaxial layer pattern defines a gate forming region that exposes the silicon substrate between the pair of first source/drain regions. A first gate insulation layer is disposed on the silicon substrate in the gate forming region. A second gate insulation layer is disposed on a sidewall of the first silicon epitaxial layer pattern. A second silicon epitaxial layer pattern is disposed in the gate forming region and on the first silicon epitaxial layer pattern. A pair of second source/drain regions is disposed on the second silicon epitaxial layer pattern. A third gate insulation layer exposes the second silicon epitaxial layer pattern in the gate forming region and covers the pair of second source/drain regions. A gate is disposed on the second silicon epitaxial layer pattern in the gate forming region.
摘要翻译：半导体器件包括设置在硅衬底上的一对第一源极/漏极区域。第一硅外延层图案限定了在一对第一源极/漏极区域之间暴露硅衬底的栅极形成区域。第一栅极绝缘层设置在栅极形成区域中的硅衬底上。第二栅极绝缘层设置在第一硅外延层图案的侧壁上。在栅极形成区域和第一硅外延层图案上设置第二硅外延层图案。一对第二源极/漏极区域设置在第二硅外延层图案上。第三栅极绝缘层在栅极形成区域中暴露第二硅外延层图案并覆盖该对第二源极/漏极区域。在栅极形成区域中的第二硅外延层图案上设置栅极。

3. 发明授权

US07312493B2 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US07312493B2
公开(公告)日：2007-12-25
申请号：US11607328
申请日：2006-11-30
申请人： Tae-Hong Lim
发明人： Tae-Hong Lim
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/78642 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device having a vertical gate and method of manufacturing the same are disclosed. An example semiconductor device includes a pair of first source/drain regions formed apart from each other by a predetermined distance on a silicon substrate, a first silicon epitaxial layer formed on the pair of first source/drain regions, a vertical gate insulation layer formed at both sidewalls of the first silicon epitaxial layer, and a second silicon epitaxial layers formed on the first silicon epitaxial layer and on the gate insulation layer. The example device includes a pair of second source/drain regions formed in the second silicon epitaxial layer formed on the first silicon epitaxial layer, at positions above the pair of first source/drain regions, and a plurality of vertical gates respectively connected to the second silicon epitaxial layer formed on the gate insulation layer and to the pair of second source/drain regions.

4. 发明申请

US20070102758A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070102758A1
公开(公告)日：2007-05-10
申请号：US11551375
申请日：2006-10-20
申请人： Tae Hong Lim
发明人： Tae Hong Lim
IPC分类号： H01L29/94
CPC分类号： H01L29/66583 , H01L21/28238 , H01L29/4236 , H01L29/66621 , H01L29/7834
摘要： A semiconductor device may include a semiconductor substrate having a recessed surface, a gate insulating layer formed on the recessed surface of the semiconductor substrate, a gate electrode formed on the gate insulating layer, and a source/drain area formed at both sides of the gate electrode, according to embodiments.
摘要翻译：半导体器件可以包括具有凹面的半导体衬底，形成在半导体衬底的凹表面上的栅极绝缘层，形成在栅极绝缘层上的栅极电极和形成在栅极两侧的源极/漏极区域电极。

5. 发明申请

US20060264399A1 Compositions for breast implant filling and methods of use 有权
标题翻译：用于乳房植入物填充的组合物和使用方法
公开(公告)号：US20060264399A1
公开(公告)日：2006-11-23
申请号：US11299644
申请日：2005-12-12
申请人： Tae-Hong Lim , Joon Park , Jin Lee , Seok-Jo Yang , Jaehyun Kim , Jin Cho
发明人： Tae-Hong Lim , Joon Park , Jin Lee , Seok-Jo Yang , Jaehyun Kim , Jin Cho
IPC分类号： A61F2/12 , A61F2/02
CPC分类号： A61L27/52 , A61F2/12 , A61L27/18 , C08L71/02
摘要： The methods and compositions disclosed herein describes a solution containing at least one block co-polymer that is a liquid at lower temperatures and transitions to a gel at higher temperatures. The compositions are useful, for example, as an alternative to saline or silicone-gel as fillers for prostheses.
摘要翻译：本文公开的方法和组合物描述了含有至少一种嵌段共聚物的溶液，其在较低温度下为液体并在较高温度下转变为凝胶。组合物可用作例如作为假体填充剂的盐水或硅凝胶的替代物。

6. 发明申请

US20100075162A1 IMPLANTS COMPRISING BIODEGRADABLE METALS AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：包含生物可降解金属的植入物及其制造方法
公开(公告)号：US20100075162A1
公开(公告)日：2010-03-25
申请号：US12441053
申请日：2007-09-21
申请人： Seok-Jo Yang , Hyun-Kwang Seok , Jung-Gu Kim , Tae-Hong Lim , Kyeong-Ho Baik , Yu-Chan Kim , Ja-Kyo Koo
发明人： Seok-Jo Yang , Hyun-Kwang Seok , Jung-Gu Kim , Tae-Hong Lim , Kyeong-Ho Baik , Yu-Chan Kim , Ja-Kyo Koo
IPC分类号： B32B15/04 , C22C23/00 , C22C23/04 , B22D21/00 , B05D1/00 , B22D25/00
CPC分类号： A61F2/30767 , A61B17/68 , A61B17/80 , A61C8/0012 , A61F2/06 , A61F2/28 , A61F2/3094 , A61F2/36 , A61F2/3662 , A61F2/442 , A61F2002/30062 , A61F2002/30064 , A61F2002/30957 , A61F2002/3631 , A61F2210/0004 , A61F2240/001 , A61F2240/004 , A61F2310/00023 , A61F2310/00041 , A61F2310/00425 , A61L27/047 , A61L27/306 , A61L27/58 , Y10T428/31678
摘要： The present invention provides an implant consisting of a biodegradable magnesium-based alloy or partially applied with the magnesium-based alloy, and a method for manufacturing the same. The implant according to the present invention is biodegradable, in which its biodegradation rate can be easily controlled, and the implant has excellent strength and interfacial strength to an osseous tissue.
摘要翻译：本发明提供一种由可生物降解的镁基合金或部分涂覆有镁基合金的植入物及其制造方法。根据本发明的植入物是可生物降解的，其中可以容易地控制其生物降解速率，并且植入物对于骨组织具有优异的强度和界面强度。

7. 发明授权

US07319060B2 Semiconductor device and method of manufacturing the semiconductor device 失效
公开(公告)号：US07319060B2
公开(公告)日：2008-01-15
申请号：US11313852
申请日：2005-12-22
申请人： Tae-Hong Lim
发明人： Tae-Hong Lim
IPC分类号： H01L21/336
CPC分类号： H01L29/66553 , H01L21/823437 , H01L21/823462 , H01L21/823487 , H01L29/66787
摘要： A semiconductor device includes a pair of first source/drain regions disposed on a silicon substrate. A first silicon epitaxial layer pattern defines a gate forming region that exposes the silicon substrate between the pair of first source/drain regions. A first gate insulation layer is disposed on the silicon substrate in the gate forming region. A second gate insulation layer is disposed on a sidewall of the first silicon epitaxial layer pattern. A second silicon epitaxial layer pattern is disposed in the gate forming region and on the first silicon epitaxial layer pattern. A pair of second source/drain regions is disposed on the second silicon epitaxial layer pattern. A third gate insulation layer exposes the second silicon epitaxial layer pattern in the gate forming region and covers the pair of second source/drain regions. A gate is disposed on the second silicon epitaxial layer pattern in the gate forming region.

8. 发明授权

US07160778B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07160778B2
公开(公告)日：2007-01-09
申请号：US11314135
申请日：2005-12-21
申请人： Tae-Hong Lim
发明人： Tae-Hong Lim
IPC分类号： H01L21/336
CPC分类号： H01L29/78642 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device having a vertical gate and method of manufacturing the same are disclosed. An example semiconductor device includes a pair of first source/drain regions formed apart from each other by a predetermined distance on a silicon substrate, a first silicon epitaxial layer formed on the pair of first source/drain regions, a vertical gate insulation layer formed at both sidewalls of the first silicon epitaxial layer, and a second silicon epitaxial layers formed on the first silicon epitaxial layer and on the gate insulation layer. The example device includes a pair of second source/drain regions formed in the second silicon epitaxial layer formed on the first silicon epitaxial layer, at positions above the pair of first source/drain regions, and a plurality of vertical gates respectively connected to the second silicon epitaxial layer formed on the gate insulation layer and to the pair of second source/drain regions.
摘要翻译：公开了一种具有垂直栅极的半导体器件及其制造方法。一种示例性半导体器件包括在硅衬底上彼此分开形成预定距离的一对第一源极/漏极区域，形成在该对第一源极/漏极区域上的第一硅外延层，形成在第一源极/漏极区域上的垂直栅极绝缘层第一硅外延层的两个侧壁和形成在第一硅外延层上和栅极绝缘层上的第二硅外延层。示例性器件包括形成在第一硅外延层上形成的第二硅外延层中的一对第二源极/漏极区，位于该对第一源极/漏极区上方的位置处，以及多个垂直栅极，分别连接到第二硅硅外延层，形成在栅极绝缘层和一对第二源极/漏极区上。

9. 发明授权

US07507647B2 Method of manufacturing a high voltage semiconductor device including a deep well and a gate oxide layer simultaneously 失效
标题翻译：同时制造包括深阱和栅极氧化物层的高电压半导体器件的方法
公开(公告)号：US07507647B2
公开(公告)日：2009-03-24
申请号：US11313693
申请日：2005-12-22
申请人： Tae-Hong Lim
发明人： Tae-Hong Lim
IPC分类号： H01L21/425
CPC分类号： H01L21/823878 , H01L21/823892
摘要： A method of manufacturing a high voltage semiconductor device including forming a P-type region implanted with P-type impurities and an N-type region implanted with N-type impurities in a silicon substrate. The method further includes forming a silicon nitride layer pattern and a pad oxide layer pattern to expose a surface of the silicon substrate, forming a trench by etching the exposed silicon substrate using the silicon nitride layer pattern as an etch mask, forming a trench oxide layer pattern in the trench by removing the silicon nitride layer pattern and the pad oxide layer pattern, and simultaneously forming a deep P-well and a deep N-well by driving P-type impurities in the P-type region and N-type impurities in the N-type region into the silicon substrate, while forming a gate oxide layer on a silicon substrate including the trench oxide layer pattern.
摘要翻译：一种制造高电压半导体器件的方法，包括在硅衬底中形成注入了P型杂质的P型区域和注入N型杂质的N型区域。该方法还包括形成氮化硅层图案和焊盘氧化物层图案以暴露硅衬底的表面，通过使用氮化硅层图案蚀刻暴露的硅衬底作为蚀刻掩模形成沟槽，形成沟槽氧化物层通过去除氮化硅层图案和焊盘氧化物层图案在沟槽中形成图案，并且通过驱动P型区域中的P型杂质和N型杂质同时形成深P阱和深N阱同时在包括沟槽氧化物层图案的硅衬底上形成栅极氧化层，形成硅衬底的N型区域。

10. 发明申请

US20080067582A1 Semiconductor device and method of manufacturing the semiconductor device 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080067582A1
公开(公告)日：2008-03-20
申请号：US11984012
申请日：2007-11-13
申请人： Tae-Hong Lim
发明人： Tae-Hong Lim
IPC分类号： H01L29/78
CPC分类号： H01L29/66553 , H01L21/823437 , H01L21/823462 , H01L21/823487 , H01L29/66787
摘要： A semiconductor device includes a pair of first source/drain regions disposed on a silicon substrate. A first silicon epitaxial layer pattern defines a gate forming region that exposes the silicon substrate between the pair of first source/drain regions. A first gate insulation layer is disposed on the silicon substrate in the gate forming region. A second gate insulation layer is disposed on a sidewall of the first silicon epitaxial layer pattern. A second silicon epitaxial layer pattern is disposed in the gate forming region and on the first silicon epitaxial layer pattern. A pair of second source/drain regions is disposed on the second silicon epitaxial layer pattern. A third gate insulation layer exposes the second silicon epitaxial layer pattern in the gate forming region and covers the pair of second source/drain regions. A gate is disposed on the second silicon epitaxial layer pattern in the gate forming region.
摘要翻译：半导体器件包括设置在硅衬底上的一对第一源极/漏极区域。第一硅外延层图案限定了在一对第一源极/漏极区域之间暴露硅衬底的栅极形成区域。第一栅极绝缘层设置在栅极形成区域中的硅衬底上。第二栅极绝缘层设置在第一硅外延层图案的侧壁上。在栅极形成区域和第一硅外延层图案上设置第二硅外延层图案。一对第二源极/漏极区域设置在第二硅外延层图案上。第三栅极绝缘层在栅极形成区域中暴露第二硅外延层图案并覆盖该对第二源极/漏极区域。在栅极形成区域中的第二硅外延层图案上设置栅极。

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