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91. 发明申请

US20170287847A1 INTEGRATED CIRCUIT PACKAGE HAVING INTEGRATED EMI SHIELD 审中-公开
公开(公告)号：US20170287847A1
公开(公告)日：2017-10-05
申请号：US15088857
申请日：2016-04-01
申请人： Rajendra C. Dias , Robert L. Sankman , Joshua D. Heppner , Mitul B. Modi , Yoshihiro Tomita
发明人： Rajendra C. Dias , Robert L. Sankman , Joshua D. Heppner , Mitul B. Modi , Yoshihiro Tomita
IPC分类号： H01L23/552 , H01L21/56 , H01L23/538 , H01L21/48 , H01L23/498 , H01L23/31
CPC分类号： H01L23/552 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/5389 , H01L2224/16227 , H01L2924/15153 , H01L2924/15311 , H01L2924/15331 , H01L2924/3025
摘要： Apparatus and methods are provided for an integrated circuit package that includes an integrated EMI shield. In an example, an integrated circuit package can include an integrated circuit mounted to a substrate via connections on the bottom surface of the integrated circuit, a conductive fence surrounding side surfaces of the integrated circuit, a conductive film coupled to the conductive fence, the film located above a top surface of the integrated circuit and coextensive with a footprint defined by the conductive fence.

92. 发明授权

US08134231B2 Semiconductor chip and semiconductor device 有权
标题翻译：半导体芯片和半导体器件
公开(公告)号：US08134231B2
公开(公告)日：2012-03-13
申请号：US12348543
申请日：2009-01-05
申请人： Hikari Sano , Yoshihiro Tomita , Takahiro Nakano
发明人： Hikari Sano , Yoshihiro Tomita , Takahiro Nakano
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L27/14618 , H01L23/3677 , H01L23/481 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L2224/02351 , H01L2224/02372 , H01L2224/0401 , H01L2224/05 , H01L2224/05548 , H01L2224/06181 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2924/014
摘要： A semiconductor chip, including: a substrate including an front surface; an integrated circuit formed on the front surface and including a plurality of semiconductor elements; and a heat-radiating plug formed in a region of the substrate corresponding to at least one of the semiconductor elements. The heat-radiating plug is made of a material having a thermal conductivity greater than that of the substrate formed in a non-penetrating hole having its opening on a reverse surface of the substrate.
摘要翻译：一种半导体芯片，包括：包括前表面的基板; 形成在所述前表面上且包括多个半导体元件的集成电路; 以及形成在所述基板的与所述半导体元件中的至少一个相对应的区域中的散热塞。散热塞由具有大于在其基板的背面上具有开口的非穿透孔中形成的基板的热导率的材料制成。

93. 发明授权

US08110920B2 In-package microelectronic apparatus, and methods of using same 有权
标题翻译：包装内微电子装置及其使用方法
公开(公告)号：US08110920B2
公开(公告)日：2012-02-07
申请号：US12455762
申请日：2009-06-05
申请人： Sriram Dattaguru , Lesley A. Polka Wood , Yoshihiro Tomita , Kinya Ichikawa , Robert L. Sankman
发明人： Sriram Dattaguru , Lesley A. Polka Wood , Yoshihiro Tomita , Kinya Ichikawa , Robert L. Sankman
IPC分类号： H01L23/34 , H05K1/16
CPC分类号： H01L25/0657 , H01L23/5384 , H01L23/5389 , H01L24/48 , H01L24/82 , H01L25/18 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/06517 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01065 , H01L2924/14 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.
摘要翻译：用于处理器的安装基板包括裸片侧和在裸片侧配置有处理器占位面的平台侧。处理器占用面积耦合到至少一个处理器互连，并且微电子管芯嵌入在安装衬底中。微电子管芯耦合到处理器互连，并且待处理器占用的处理器之间的通信速率在10Gb / s至1Tb / s之间。

94. 发明授权

US07927997B2 Flip-chip mounting method and bump formation method 有权
标题翻译：倒装芯片安装方法和凸块形成方法
公开(公告)号：US07927997B2
公开(公告)日：2011-04-19
申请号：US11579299
申请日：2006-03-07
申请人： Koichi Hirano , Seiji Karashima , Takashi Ichiryu , Yoshihiro Tomita , Seiichi Nakatani
发明人： Koichi Hirano , Seiji Karashima , Takashi Ichiryu , Yoshihiro Tomita , Seiichi Nakatani
IPC分类号： H01L21/445
CPC分类号： H01L21/563 , B23K35/0244 , H01L21/67144 , H01L21/6835 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/75 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/1131 , H01L2224/13099 , H01L2224/1319 , H01L2224/133 , H01L2224/16 , H01L2224/75 , H01L2224/83192 , H01L2224/8321 , H01L2224/83815 , H01L2224/83886 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01056 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/18161 , H01L2924/30105 , H05K3/323 , H05K3/3436 , H05K3/3484 , H05K2201/10977 , H05K2203/1361 , Y02P70/613 , Y10T29/53178 , H01L2224/05599
摘要： To provide a flip-chip mounting method and a bump formation method applicable to flip-chip mounting of a next generation LSI and having high productivity and high reliability.A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are dipped in a dipping bath 40 containing a melted resin 14 including melted solder particles for a given period of time. In this dipping process, the melted solder particles self-assemble between the connection terminals 11 of the circuit board 21 and the electrode terminals 12 of the semiconductor chip 20, so as to form connectors 22 between these terminals. Thereafter, the semiconductor chip 20 and the circuit board 21 are taken out of the dipping bath 40, and the melted resin 14 having permeated into the gap between the semiconductor chip 20 and the circuit board 21 is cured, so as to complete a flip-chip mounting body.
摘要翻译：提供适用于下一代LSI的倒装安装并具有高生产率和高可靠性的倒装芯片安装方法和凸块形成方法。具有多个电极端子12的半导体芯片20被保持为具有多个连接端子11的电路板21，其间设置有给定的间隙，并且在该状态下将半导体芯片20和电路板21浸入浸渍浴40含有包含熔融的焊料颗粒的熔融树脂14一段给定的时间。在该浸渍过程中，熔融的焊料颗粒自组装在电路板21的连接端子11和半导体芯片20的电极端子12之间，从而在这些端子之间形成连接器22。此后，半导体芯片20和电路板21从浸渍浴40中取出，并且已经渗透到半导体芯片20和电路板21之间的间隙中的熔融树脂14固化，芯片安装体。

95. 发明授权

US07841080B2 Multi-chip packaging using an interposer with through-vias 有权
标题翻译：多芯片封装采用插入式通孔
公开(公告)号：US07841080B2
公开(公告)日：2010-11-30
申请号：US11755735
申请日：2007-05-30
申请人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
发明人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
IPC分类号： H01K3/22
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/147 , H01L25/0655 , H01L2224/81203 , H01L2224/81815 , H01L2924/10253 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49163 , Y10T29/49165 , H01L2924/00
摘要： One embodiment relates to forming a plurality of vias extending partially through a body, the vias including sidewalls defined by the body. An insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. A plurality of electronic elements are coupled to the second metal pads. After the coupling the elements, the body is thinned through a lower surface. A portion of the insulating layer in the vias is removed and the electrically conductive layer is coupled to a substrate.
摘要翻译：一个实施例涉及形成多个部分地穿过主体的通孔，通孔包括由主体限定的侧壁。绝缘层形成在主体的侧壁和上表面上。在绝缘层上形成导电层，导电层限定上表面上的第一金属焊盘和与第一金属焊盘接触的第二金属焊盘，第二金属焊盘具有比第一金属焊盘更致密的间距。在相邻的第一金属焊盘之间和相邻的第二金属焊盘之间形成介电层。多个电子元件耦合到第二金属焊盘。在连接元件之后，主体通过下表面变薄。去除通孔中的绝缘层的一部分，并且将导电层耦合到衬底。

96. 发明授权

US07726545B2 Flip chip mounting process and bump-forming process using electrically-conductive particles as nuclei 有权
标题翻译：使用导电颗粒作为核的倒装芯片安装工艺和凸块形成工艺
公开(公告)号：US07726545B2
公开(公告)日：2010-06-01
申请号：US11886311
申请日：2006-03-13
申请人： Takashi Ichiryu , Seiichi Nakatani , Seiji Karashima , Yoshihiro Tomita , Koichi Hirano , Toshio Fujii
发明人： Takashi Ichiryu , Seiichi Nakatani , Seiji Karashima , Yoshihiro Tomita , Koichi Hirano , Toshio Fujii
IPC分类号： B23K31/02 , B23K31/00 , H01L21/44
CPC分类号： H05K3/3436 , H01L21/4853 , H01L21/6835 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/81 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/11005 , H01L2224/1152 , H01L2224/11524 , H01L2224/16 , H01L2224/73104 , H01L2224/73204 , H01L2224/81801 , H01L2224/83192 , H01L2224/83886 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01056 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H05K3/323 , H05K3/3484 , H05K2201/10977 , H05K2203/083 , H05K2203/087 , Y02P70/613 , Y10T29/49126 , H01L2224/13099 , H01L2224/29099 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A flip chip mounting process or a bump-forming process according to the present invention is characterized in that electrically-conductive particles are fixed on electrodes formed on an electronic component. A composition comprising solder powder, a convection additive and a resin component is supplied onto a surface of the electronic component, the surface is provided with the electrodes. The supplied composition is heated up to a temperature enabling the solder powder to melt. As a result, the convection additive boils or is decomposed so as to generate a gas. The generated gas produces a convection phenomenon within the supplied composition. Since the convection phenomenon promotes the movement of the solder powder, the solder powder can move freely within the composition. The electrically-conductive particles serve as nuclei for the solder powder to self-assemble and grow. As a result, the molten solder powder is allowed to self-assemble and grow in the vicinity of the electrically-conductive particles, which leads to a formation of connections or bumps.
摘要翻译：根据本发明的倒装芯片安装工艺或凸块形成工艺的特征在于，导电颗粒固定在形成在电子部件上的电极上。将包含焊料粉末，对流添加剂和树脂组分的组合物供应到电子部件的表面上，该表面设置有电极。将所提供的组合物加热到使焊料粉末熔化的温度。结果，对流添加剂沸腾或分解以产生气体。所产生的气体在所提供的组合物内产生对流现象。由于对流现象促使焊料粉末的移动，焊料粉末可以在组合物内自由移动。导电颗粒用作焊料粉末的自组装和生长的核。结果，允许熔融焊料粉末在导电颗粒附近自组装和生长，这导致连接或凸块的形成。

97. 发明申请

US20090300448A1 SCAN FLIP-FLOP DEVICE 审中-公开
标题翻译：扫描FLIP-FLOP设备
公开(公告)号：US20090300448A1
公开(公告)日：2009-12-03
申请号：US12466600
申请日：2009-05-15
申请人： Yoshihiro Tomita , Yukinori Uchino
发明人： Yoshihiro Tomita , Yukinori Uchino
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318541
摘要： A scan flip-flop device has a scan flip-flop, a Nch insulated gate field effect transistor and a Pch insulated gate field effect transistor. The Nch insulated gate field effect transistor is located on an output side the scan flip-flop. The Nch insulated gate field effect transistor turns off and dose not output a signal when a test enable signal is in a disable mode. The Pch insulated gate field effect transistor is located between a higher voltage source and an output side of the Nch insulated gate field effect transistor. The Pch insulated gate field effect transistor turns on when a test enable signal is in a disable mode. The Pch insulated gate field effect transistor sets a SO port at a high level voltage.
摘要翻译：扫描触发器装置具有扫描触发器，Nch绝缘栅场效应晶体管和Pch绝缘栅场效应晶体管。 Nch绝缘栅场效应晶体管位于扫描触发器的输出侧。当测试使能信号处于禁用模式时，Nch绝缘栅场效应晶体管截止并且不输出信号。 Pch绝缘栅场效应晶体管位于Nch绝缘栅场效应晶体管的较高电压源和输出侧之间。当测试使能信号处于禁止模式时，Pch绝缘栅场效应晶体管导通。 Pch绝缘栅场效应晶体管将SO端口设置在高电平电压。

98. 发明申请

US20090242940A1 SENSOR DEVICE AND FABRICATION METHOD FOR THE SAME 有权
标题翻译：传感器装置及其制造方法
公开(公告)号：US20090242940A1
公开(公告)日：2009-10-01
申请号：US12404923
申请日：2009-03-16
申请人： Masanori MINAMIO , Yoshihiro Tomita
发明人： Masanori MINAMIO , Yoshihiro Tomita
IPC分类号： H01L29/84 , H01L21/00
CPC分类号： H01L21/67248 , H01L21/67063
摘要： The sensor device includes: a converter body made of silicon in the shape of a rhombus in plan, the converter body having an opening in the shape of a hexagon in plan; a substrate for holding the converter body; a movable film formed on the opening; a converter electrode formed on the converter body; and a substrate electrode formed on the substrate, the substrate electrode being electrically connected with the converter electrode. The opening is placed so that four of the six sides of the hexagon extend along the four sides of the rhombus of the converter body.
摘要翻译：该传感器装置包括：平面内呈菱形形状的硅转换体，该转换体具有平面形状的六边形开口; 用于保持转换器主体的基板; 形成在开口上的可动膜; 形成在所述转换器主体上的转换器电极; 以及形成在所述基板上的基板电极，所述基板电极与所述转换器电极电连接。放置开口使得六边形的六个边中的四个沿着转换器主体的菱形的四边延伸。

99. 发明申请

US20090059055A1 OPTICAL DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：光学装置及其制造方法
公开(公告)号：US20090059055A1
公开(公告)日：2009-03-05
申请号：US12195081
申请日：2008-08-20
申请人： Takahiro Nakano , Yoshihiro Tomita , Hikari Sano
发明人： Takahiro Nakano , Yoshihiro Tomita , Hikari Sano
IPC分类号： H04N5/225
CPC分类号： H04N5/2253 , H01L27/14618 , H01L27/14627 , H01L27/14687 , H01L2224/02372 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05548 , H01L2224/0557 , H01L2224/11 , H01L2924/00014 , H04N5/2254 , H01L2224/05099
摘要： An optical device includes: an optical element including an imaging region, a peripheral circuit region formed at the rim of the imaging region and including a plurality of electrode portions, and a plurality of microlenses formed on the imaging region; a plurality of through-hole electrodes connected to the respective electrode portions and formed through the semiconductor substrate along the thickness of the semiconductor substrate; a plurality of metal interconnects connected to the respective through-hole electrodes and formed on a back surface of the semiconductor substrate opposite to a principal surface of the semiconductor substrate; an adhesive member formed on a surface of the optical element and made of a resin; and a transparent board bonded to the optical element with the adhesive member interposed therebetween. The transparent board has a planar shape larger than that of the optical element.
摘要翻译：光学装置包括：光学元件，包括成像区域，形成在成像区域的边缘处并包括多个电极部分的外围电路区域和形成在成像区域上的多个微透镜; 多个通孔电极，其连接到各个电极部分并沿半导体衬底的厚度形成在半导体衬底上; 多个金属互连件，连接到相应的通孔电极并形成在与半导体衬底的主表面相对的半导体衬底的背面上; 形成在所述光学元件的表面上并由树脂制成的粘合部件; 以及粘合到光学元件上的透明板，其间插入有粘合构件。透明板具有比光学元件大的平面形状。

100. 发明申请

US20090034760A1 ELECTRONIC COMPONENT, FABRICATION METHOD FOR THE SAME AND ELECTRONIC DEVICE HAVING THE SAME 审中-公开
标题翻译：电子元件，其制造方法和具有该电子元件的电子器件
公开(公告)号：US20090034760A1
公开(公告)日：2009-02-05
申请号：US12180875
申请日：2008-07-28
申请人： Masanori MINAMIO , Yoshihiro Tomita , Toshiyuki Fukuda
发明人： Masanori MINAMIO , Yoshihiro Tomita , Toshiyuki Fukuda
IPC分类号： H04R1/00
CPC分类号： H04R19/016 , H01G7/02 , H01L2224/48091 , H01L2224/48137 , H01L2924/01322 , H01L2924/1461 , H01L2924/3025 , H04R19/005 , H04R2499/11 , H01L2924/00 , H01L2924/00014
摘要： The electronic component includes: a fixed film; a vibration film facing the fixed film; a first electrode formed on the fixed film and having at least one first through hole in the center portion; and a second electrode formed on a portion of the vibration film corresponding to the first electrode and having at least one second through hole in the peripheral portion. An air gap communicating with the first and second through holes is formed between the fixed film and the vibration film and surrounded with a rib. At least one side hole is provided to extend in the rib surrounding the air gap from the air gap toward outside.
摘要翻译：电子部件包括：固定膜; 面向固定膜的振动膜; 第一电极，形成在所述固定膜上并且在所述中心部分中具有至少一个第一通孔; 以及第二电极，形成在所述振动膜的与所述第一电极对应的部分上，并且在所述周边部分中具有至少一个第二通孔。在固定膜和振动膜之间形成有与第一和第二通孔连通的气隙，并且被肋条包围。至少一个侧孔设置成在从气隙朝向外侧的气隙周围的肋中延伸。

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