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91. 发明授权

US09252219B2 Insulated gate bipolar transistor with a lateral gate structure and gallium nitride substrate 有权
标题翻译：具有横向栅极结构和氮化镓衬底的绝缘栅双极晶体管
公开(公告)号：US09252219B2
公开(公告)日：2016-02-02
申请号：US14464220
申请日：2014-08-20
申请人： Chih-Fang Huang , Tsung-Yi Huang , Chien-Wei Chiu , Tsung-Yu Yang , Ting-Fu Chang , Tsung-Chieh Hsiao , Ya-Hsien Liu , Po-Chin Peng
发明人： Chih-Fang Huang , Tsung-Yi Huang , Chien-Wei Chiu , Tsung-Yu Yang , Ting-Fu Chang , Tsung-Chieh Hsiao , Ya-Hsien Liu , Po-Chin Peng
IPC分类号： H01L29/73 , H01L29/66 , H01L29/20 , H01L29/423 , H01L29/778
CPC分类号： H01L29/66325 , H01L27/0722 , H01L29/1095 , H01L29/2003 , H01L29/201 , H01L29/42316 , H01L29/66462 , H01L29/7787
摘要： The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.
摘要翻译：本发明公开了一种绝缘栅双极晶体管（IGBT）及其制造方法。 IGBT包括：氮化镓（GaN）衬底，具有第一导电类型的第一GaN层，具有第一导电类型的第二GaN层，具有第二导电类型或本征导电类型的第三GaN层，以及栅极形成在GaN衬底上。第一GaN层形成在GaN衬底上并具有垂直于GaN衬底的侧壁。第二GaN层形成在GaN衬底上，并通过栅极与第一GaN层分离。第三GaN层形成在第一GaN层上，并通过第一GaN层与GaN衬底分离。门具有在横向方向上与侧壁相邻的侧板以控制通道。

92. 发明授权

US09245945B1 Semiconductor device having weak current channel 有权
标题翻译：具有弱电流通道的半导体器件
公开(公告)号：US09245945B1
公开(公告)日：2016-01-26
申请号：US14534955
申请日：2014-11-06
申请人： Tsung-Yi Huang , Chien-Wei Chiu , Huang-Ping Chu , Chien-Kai Chang
发明人： Tsung-Yi Huang , Chien-Wei Chiu , Huang-Ping Chu , Chien-Kai Chang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/06 , H01L29/78
CPC分类号： H01L29/7833 , H01L29/063 , H01L29/0653 , H01L29/0692 , H01L29/42368 , H01L29/7816
摘要： The invention provides a semiconductor device having a weak current channel. The semiconductor device includes a gate, a source and a drain. There are a plurality of insulation layers and a plurality of first conductive type lightly doped regions alternatingly arranged between the gate and the drain; each of the first conductive type lightly doped regions providing a weak current channel between the source and the drain. When the gate is in a relatively low voltage range, the weak current channel is conducted; when the gate is in a relatively high voltage range, the weak current channel is not conducted.
摘要翻译：本发明提供一种具有弱电流通道的半导体器件。半导体器件包括栅极，源极和漏极。存在多个绝缘层和交替布置在栅极和漏极之间的多个第一导电类型轻掺杂区域; 每个第一导电类型的轻掺杂区域在源极和漏极之间提供弱电流通道。当栅极处于相对较低的电压范围时，进行弱电流通道; 当栅极处于相对较高的电压范围时，不会导通弱电流通道。

93. 发明授权

US09105491B2 Semiconductor structure and semiconductor device having the same 有权
标题翻译：半导体结构和具有相同的半导体器件
公开(公告)号：US09105491B2
公开(公告)日：2015-08-11
申请号：US14041336
申请日：2013-09-30
申请人： Tsung-Yi Huang
发明人： Tsung-Yi Huang
IPC分类号： H01L29/66 , H01L29/06 , H01L29/78
CPC分类号： H01L29/0684 , H01L21/823892 , H01L29/0646 , H01L29/0878 , H01L29/1083 , H01L29/36 , H01L29/78 , H01L29/7816
摘要： The invention provides a semiconductor structure and a semiconductor device having such semiconductor structure. The semiconductor structure includes: a substrate; a first well having a first conductivity type, which is provided on the substrate; a second well having a second conductivity type and contacting the first well at a boundary in between in a lateral direction; and a plurality of mitigation regions having the first conductivity type or the second conductivity type, provided in the first well and being close to the boundary in a lateral direction and penetrating the first well in a vertical direction.
摘要翻译：本发明提供一种具有这种半导体结构的半导体结构和半导体器件。半导体结构包括：基板; 具有第一导电类型的第一阱，其设置在基板上; 第二阱具有第二导电类型，并且在横向方向上的边界处接触第一阱; 以及具有第一导电类型或第二导电类型的多个缓和区，设置在第一阱中并且在横向方向上接近边界并且在垂直方向上穿透第一阱。

94. 发明申请

US20150130067A1 OHMIC CONTACT STRUCTURE AND SEMICONDUCTOR DEVICE HAVING THE SAME 审中-公开
标题翻译： OHMIC接触结构和具有相同的半导体器件
公开(公告)号：US20150130067A1
公开(公告)日：2015-05-14
申请号：US14076768
申请日：2013-11-11
申请人： Chien-Wei Chiu , Ting-Wei Liao , Chieh-Hsiung Kuan , Tsung-Yi Huang , Tsung-Yu Yang
发明人： Chien-Wei Chiu , Ting-Wei Liao , Chieh-Hsiung Kuan , Tsung-Yi Huang , Tsung-Yu Yang
IPC分类号： H01L29/41 , H01L29/45
CPC分类号： H01L29/45 , H01L21/28512 , H01L21/28525 , H01L21/28575 , H01L29/0688 , H01L29/2003 , H01L29/41725 , H01L29/452 , H01L29/872
摘要： This invention provides an ohmic contact structure including: a semiconductor substrate having a top surface which includes a plurality of micro-structures; and a conductive layer, which is formed on the micro-structures. An ohmic contact is formed by the conductive layer and the semiconductor substrate. The present invention also provides a semiconductor device having the ohmic contact structure.
摘要翻译：本发明提供一种欧姆接触结构，包括：半导体衬底，其具有包括多个微结构的顶表面; 以及形成在微结构上的导电层。由导电层和半导体衬底形成欧姆接触。本发明还提供一种具有欧姆接触结构的半导体器件。

95. 发明授权

US09018703B2 Hybrid high voltage device and manufacturing method thereof 有权
标题翻译：混合高压器件及其制造方法
公开(公告)号：US09018703B2
公开(公告)日：2015-04-28
申请号：US14176973
申请日：2014-02-10
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L29/66 , H01L29/78 , H01L29/423 , H01L29/40 , H01L29/06
CPC分类号： H01L29/7817 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/402 , H01L29/42368 , H01L29/4238 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.
摘要翻译：本发明公开了一种混合式高压装置及其制造方法。混合高压器件形成在第一导电型衬底中，并且包括至少一个横向双扩散金属氧化物半导体（LDMOS）器件区域和至少一个通气器件区域，其中LDMOS器件区域和通气器件区域被连接在宽度方向上以交替的顺序布置。此外，LDMOS器件区域和通风装置区域的相应的高压井，源极，漏极，体区和栅极分别彼此连接。

96. 发明授权

US09012989B2 High voltage device and manufacturing method thereof 有权
标题翻译：高压器件及其制造方法
公开(公告)号：US09012989B2
公开(公告)日：2015-04-21
申请号：US14483520
申请日：2014-09-11
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L29/66 , H01L29/78 , H01L21/266 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423
CPC分类号： H01L29/0878 , H01L21/266 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/086 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions.
摘要翻译：本发明公开了一种高压器件及其制造方法。高压器件形成在第一导电型衬底中，其中衬底包括限定器件区域的隔离区域。高电压装置包括：位于器件区域中的掺杂有第二导电类型杂质的漂移区; 在器件区域和衬底的表面上的栅极; 以及在栅极的不同侧的器件区域中的第二导电类型源极和漏极。从俯视图，漂移区域的第二导电型杂质的浓度沿水平方向和垂直方向大致周期性地分布。

97. 发明申请

US20150091087A1 METAL OXIDE SEMICONDUCTOR (MOS) DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：金属氧化物半导体（MOS）器件及其制造方法
公开(公告)号：US20150091087A1
公开(公告)日：2015-04-02
申请号：US14456734
申请日：2014-08-11
申请人： Tsung-Yi Huang
发明人： Tsung-Yi Huang
IPC分类号： H01L29/78 , H01L29/66 , H01L29/08 , H01L21/265
CPC分类号： H01L29/66492 , H01L29/1045 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： The present invention discloses a metal oxide semiconductor (MOS) device and a manufacturing method thereof. The MOS device is formed in a substrate with an upper surface and it includes: an isolation region, a well region, a gate, a lightly-doped-source (LDS), a lightly-doped-drain (LDD), a source, and a drain. The isolation region defines an operation region. The gate includes: a dielectric layer, a stack layer, and a spacer layer, wherein the stack layer separates the operation region to a first side and a second side. The LDS with a first conductive type, is formed in the substrate beneath the upper surface, and at least part of the LDS overlaps the stack layer from a top view. The source with a second conductive type overlaps the spacer layer at the first side. The conductive types of the LDS and the source are different to mitigate the threshold voltage roll-off.
摘要翻译：本发明公开了一种金属氧化物半导体（MOS）器件及其制造方法。 MOS器件形成在具有上表面的衬底中，并且其包括：隔离区，阱区，栅极，轻掺杂源（LDS），轻掺杂漏极（LDD），源极，和排水。隔离区域定义一个操作区域。栅极包括：电介质层，堆叠层和间隔层，其中堆叠层将操作区域分离成第一侧和第二侧。具有第一导电类型的LDS形成在上表面下方的基板中，并且至少部分LDS从顶视图与堆叠层重叠。具有第二导电类型的源在第一侧与间隔层重叠。 LDS和源的导电类型不同，以减轻阈值电压下降。

98. 发明授权

US08859375B2 High voltage device and manufacturing method thereof 有权
标题翻译：高压器件及其制造方法
公开(公告)号：US08859375B2
公开(公告)日：2014-10-14
申请号：US13317401
申请日：2011-10-17
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L21/336 , H01L21/266 , H01L29/08 , H01L29/78 , H01L29/06 , H01L29/423 , H01L29/66
CPC分类号： H01L29/0878 , H01L21/266 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/086 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions.
摘要翻译：本发明公开了一种高压器件及其制造方法。高压器件形成在第一导电型衬底中，其中衬底包括限定器件区域的隔离区域。高电压装置包括：位于器件区域中的掺杂有第二导电类型杂质的漂移区; 在器件区域和衬底的表面上的栅极; 以及在栅极的不同侧的器件区域中的第二导电类型源极和漏极。从俯视图，漂移区域的第二导电型杂质的浓度沿水平方向和垂直方向大致周期性地分布。

99. 发明授权

US08710551B2 High electron mobility transistor and manufacturing method thereof 有权
标题翻译：高电子迁移率晶体管及其制造方法
公开(公告)号：US08710551B2
公开(公告)日：2014-04-29
申请号：US13597599
申请日：2012-08-29
申请人： Chih-Fang Huang , Chien-Wei Chiu , Ting-Fu Chang , Tsung-Yu Yang , Tsung-Yi Huang
发明人： Chih-Fang Huang , Chien-Wei Chiu , Ting-Fu Chang , Tsung-Yu Yang , Tsung-Yi Huang
IPC分类号： H01L31/109 , H01L31/072
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/41766 , H01L29/7787
摘要： The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain.
摘要翻译：本发明公开了一种高电子迁移率晶体管（HEMT）及其制造方法。 HEMT包括半导体层，半导体层上的势垒层，阻挡层上的压电层，压电层上的栅极，栅极两侧的源极和漏极，其中半导体的每个带隙层，阻挡层和压电层部分但不完全与其它两个带隙重叠。栅极形成为用于接收栅极电压。二维电子气体（2DEG）形成在半导体层和阻挡层之间的结的一部分中，但不在压电层的至少一部分下方，其中2DEG电连接到源极和漏极。

100. 发明授权

US08686500B2 Double diffused metal oxide semiconductor device and manufacturing method thereof 有权
标题翻译：双扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US08686500B2
公开(公告)日：2014-04-01
申请号：US13476043
申请日：2012-05-21
申请人： Tsung-Yi Huang , Ching-Yao Yang
发明人： Tsung-Yi Huang , Ching-Yao Yang
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/7835 , H01L29/063 , H01L29/1083 , H01L29/42368 , H01L29/66681 , H01L29/7816
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device is formed in a first conductive type substrate, and includes a second conductive type high voltage well, a field oxide region, a gate, a second conductive type source, a second conductive type drain, a first conductive type body region, and a first conductive type deep well. The deep well is formed beneath and adjacent to the high voltage well in a vertical direction. The deep well and the high voltage well are defined by a same lithography process step.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件形成在第一导电型衬底中，并且包括第二导电型高电压阱，场氧化物区域，栅极，第二导电型源极，第二导电型漏极，第一导电型体区域和第一导电型深井。深井在垂直方向上形成在高压井的下方并与其相邻。深井和高压阱由相同的光刻工艺步骤定义。

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