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91. 发明授权

US5940335A Prioritizing the repair of faults in a semiconductor memory device 失效
标题翻译：对半导体存储器件中的故障进行优先排序
公开(公告)号：US5940335A
公开(公告)日：1999-08-17
申请号：US122426
申请日：1998-07-24
申请人： Toshiaki Kirihata
发明人： Toshiaki Kirihata
IPC分类号： G11C29/04 , G11C29/00 , G11C7/00
CPC分类号： G11C29/804 , G11C29/808
摘要： A variable size redundancy replacement (VSRR) arrangement for making a memory fault-tolerant. A redundancy array supporting the memory includes a plurality of variable size redundancy units, each of which encompasses a plurality of redundancy elements. The redundancy units, used for repairing faults in the memory, are independently controlled. All the redundancy elements within a repair unit are preferably replaced simultaneously. The redundancy elements in the redundancy unit are controlled by decoding address lines. The variable size that characterizes this configuration makes it possible to choose the most effective redundancy unit, and in particular, the one most closely fitting the size of the cluster of failures to be replaced. This configuration significantly reduces the overhead created by added redundancy elements and control circuitry, while improving the access speed and reducing power consumption. Finally, a fault-tolerant block redundancy controlled by a priority decoder makes it possible to use VSRR units for repairing faults in the block redundancy prior to its use for replacing a defective block within the memory.
摘要翻译：用于使存储器容错的可变大小冗余替换（VSRR）布置。支持存储器的冗余阵列包括多个可变大小的冗余单元，每个冗余单元包括多个冗余元件。用于修复存储器故障的冗余单元是独立控制的。维修单元内的所有冗余元件优选同时更换。冗余单元中的冗余元件通过解码地址线来控制。表征此配置的可变大小使得可以选择最有效的冗余单元，特别是最接近要替换的故障群集大小的冗余单元。这种配置可显着降低由添加的冗余元件和控制电路产生的开销，同时提高访问速度并降低功耗。最后，由优先级解码器控制的容错块冗余使得可以使用VSRR单元来修复块冗余中的故障，在其用于替换存储器内的有缺陷块之前。

92. 发明授权

US5848008A Floating bitline test mode with digitally controllable bitline equalizers 失效
标题翻译：具有数字可控位线均衡器的浮动位线测试模式
公开(公告)号：US5848008A
公开(公告)日：1998-12-08
申请号：US937528
申请日：1997-09-25
申请人： Toshiaki Kirihata , Hing Wong , Bozidar Krsnik
发明人： Toshiaki Kirihata , Hing Wong , Bozidar Krsnik
IPC分类号： G01R31/28 , G11C11/401 , G11C29/04 , G11C29/50 , G11C29/56 , G11C7/00
CPC分类号： G11C29/50
摘要： A method for generating a floating bitline test mode using digitally controllable bitline equalizers is provided. The method utilizes digitally controlled dummy timing cycles to detect a leaky bitline during the floating bitline test mode. A negative pulsed TEST signal is generated to cause the bitline equalizers to go low and cause the floating bitline state. The implementation of dummy timing cycles eliminates the need for additional external control of internal timings during a bitline test mode. Upon the termination of the dummy timing cycle, the normal read operation continues without interruption.
摘要翻译：提供一种使用数字可控位线均衡器产生浮动位线测试模式的方法。该方法利用数字控制的虚拟定时周期来检测浮动位线测试模式期间的泄漏位线。产生负脉冲+ E，ovs TEST + EE信号，使位线均衡器变为低电平，并导致浮置位线状态。虚拟定时周期的实现消除了在位线测试模式期间对内部定时的额外外部控制的需要。在虚拟定时周期结束时，正常读取操作继续而不中断。

93. 发明授权

US5764655A Built in self test with memory 失效
标题翻译：内置自检
公开(公告)号：US5764655A
公开(公告)日：1998-06-09
申请号：US887374
申请日：1997-07-02
申请人： Toshiaki Kirihata , Christopher D. Wait
发明人： Toshiaki Kirihata , Christopher D. Wait
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/273 , G11C29/12 , H01L21/66 , G06F11/00
CPC分类号： G06F11/2635 , G01R31/318505 , G01R31/31702
摘要： An integrated circuit chip and an electronic system are disclosed, each incorporating a self-test system. The integrated circuit chip includes capability for Built In Self Test (BIST) and a non-volatile memory where the BIST may be self-programmable. The electronic system comprises, an integrated circuit chip which includes on the chip Built In Self Test (BIST) and a non-volatile memory, together with an off-chip test target. The integrated circuit chip and the electronic system are particularly useful for simplifying the testing of electronic products both in manufacturing and in the field, and are even more particularly useful in eliminating the need for large, complex, high speed testers in the manufacturing environment, substituting instead a simple power chuck to plug the product into.
摘要翻译：公开了一种集成电路芯片和电子系统，其中包括自检系统。集成电路芯片包括内置自检（BIST）和非易失性存储器，其中BIST可以是自编程的。电子系统包括集成电路芯片，其包括芯片内置自测（BIST）和非易失性存储器，以及片外测试目标。集成电路芯片和电子系统对于简化制造和现场的电子产品的测试特别有用，并且甚至更具体地用于消除在制造环境中对大型，复杂的高速测试仪的需要，代替而是一个简单的动力卡盘来插入产品。

94. 发明授权

US5615164A Latched row decoder for a random access memory 失效
标题翻译：用于随机存取存储器的锁存行解码器
公开(公告)号：US5615164A
公开(公告)日：1997-03-25
申请号：US477063
申请日：1995-06-07
申请人： Toshiaki Kirihata , Hing Wong
发明人： Toshiaki Kirihata , Hing Wong
IPC分类号： G11C11/413 , G11C8/10 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/02 , G11C29/06 , G11C29/12 , G11C29/34 , G11C29/50 , G11C8/00
CPC分类号： G11C29/025 , G11C29/02 , G11C29/34 , G11C29/50 , G11C8/10 , G11C11/401
摘要： A latched row decoder for a Random Access Memory (RAM). The Decoder includes a set-reset latch that is set when addressed and remains set until reset by a PRE signal; address select logic; a reset device; and gated word line drives. The latch, when set, enables four word line drivers that are driven individually depending on two row address bits. During test, latched decoders may be selected sequentially and not reset, leaving drivers enabled until a test is complete. Thus some or all word lines may be driven simultaneously during test. A RAM including the latched decoder of the present invention has a normal random access mode and at least 4 test modes. The test modes are: Long t.sub.RAS word line disturb mode; toggled word line disturb mode; transfer gate stress mode; and a stress test mode.
摘要翻译：用于随机存取存储器（RAM）的锁存行解码器。解码器包括设置复位锁存器，其在寻址时被置位并保持置位，直到由PRE信号复位; 地址选择逻辑; 复位装置; 和门控驱动器。当锁存器置位时，可以根据两个行地址位单独驱动四个字线驱动器。在测试期间，锁存解码器可以顺序选择并且不复位，使驱动器启用，直到测试完成。因此，在测试期间可以同时驱动一些或所有字线。包括本发明的锁存解码器的RAM具有正常的随机存取模式和至少4个测试模式。测试模式为：长tRAS字线干扰模式; 切换字线干扰模式; 传输门应力模式; 和压力测试模式。

95. 发明授权

US5517442A Random access memory and an improved bus arrangement therefor 失效
标题翻译：随机存取存储器及其改进的总线布置
公开(公告)号：US5517442A
公开(公告)日：1996-05-14
申请号：US402790
申请日：1995-03-13
申请人： Toshiaki Kirihata , Yohji Watanabe , Hing Wong
发明人： Toshiaki Kirihata , Yohji Watanabe , Hing Wong
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409 , G11C29/00 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C29/80 , G11C7/10
摘要： The present invention is a bus arrangement for a wide I/O Random Access Memory (RAM). The bus arrangement includes a global address bus which drives row/column predecoders and redundancy comparators placed at each edge of the memory array. Two banks of sixteen data I/O (DQs), one bank for each half chip, are placed at either end of the chip providing up to a .times.32 I/O organization. The main Read/Write Data lines (RWD) are more densely populated near the chip edge than the chip center to provide .times.4 and .times.8 options, as well. A local address bus is in the open space between the RWDs to redrive the global address lines at their quarter points.
摘要翻译：本发明是用于宽I / O随机存取存储器（RAM）的总线装置。总线布置包括全局地址总线，其驱动行/列预解码器和放置在存储器阵列的每个边缘处的冗余比较器。十六个数据I / O（DQ）的两组，每个半芯片的一个存储区，放置在芯片的任一端，提供一个x32 I / O组织。主芯片读/写数据线（RWD）在芯片边缘附近比芯片中心更密集，以提供x4和x8选项。本地地址总线位于RWD之间的开放空间，以便在其四分之一点重新启动全局地址线。

96. 发明授权

US5257232A Sensing circuit for semiconductor memory with limited bitline voltage swing 失效
标题翻译：具有有限位线电压摆幅的半导体存储器的感应电路
公开(公告)号：US5257232A
公开(公告)日：1993-10-26
申请号：US847769
申请日：1992-03-05
申请人： Sang H. Dhong , Koji Kitamura , Toshiaki Kirihata , Toshio Sunaga
发明人： Sang H. Dhong , Koji Kitamura , Toshiaki Kirihata , Toshio Sunaga
IPC分类号： G11C11/409 , G11C7/06 , G11C11/407 , G11C11/4091 , G11C13/00
CPC分类号： G11C11/4091 , G11C7/065
摘要： A sensing circuit for dynamic random access memory is disclosed including a pair of bitlines precharged to a first voltage before sensing. A sense amplifier circuit is provided having one node thereof being connected to an external power supply via a switching means including pulsed sense clocks. Control means is provided and is connected to the switching means for controlling the switching means such that the voltage of the power supply is coupled to the node of the sense amplifier for activation for a predetermined period of time, thereby limiting the swing for the high-going bitline to a second voltage lower than said power supply voltage and higher than the first voltage. The reduced bit-line swings are achieved by means of the pulsed sense clocks and the pulse widths for sense clocks are determined by means of a reference bitlines connected to the control means.

97. 发明授权

US07817455B2 Random access electrically programmable e-fuse ROM 有权
标题翻译：随机存取电可编程电子熔丝ROM
公开(公告)号：US07817455B2
公开(公告)日：2010-10-19
申请号：US12065202
申请日：2006-08-30
申请人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
发明人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/165 , G11C29/027
摘要： A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at VDD while the bit line drive is switched between VDD and a higher voltage, Vp, for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current path for minimal voltage drop during fuse programming. A differential sense amplifier with a programmable reference is used for improved sense margins and can support an entire bit line rather than sense amplifiers being provided for individual fuses.
摘要翻译：一次性可编程只读存储器（OTPROM）在二维阵列中实现，这些阵列具有大规模的自杀可迁移电子保险丝。通过在VDD处工作的解码逻辑执行字线选择，同时位线驱动器在VDD和较高电压Vp之间切换，用于编程。因此，OTPROM与其他技术兼容，并且可以与其他技术集成，而无需使用成本加法器，并支持在熔丝编程期间最小化电压降的高电流路径的优化。具有可编程参考的差分读出放大器用于改进的检测余量，并且可以支持整个位线，而不是为各个保险丝提供感测放大器。

98. 发明申请

US20080316789A1 Random Access Electrically Programmable E-Fuse Rom 有权
标题翻译：随机存取电子可编程电子保险丝
公开(公告)号：US20080316789A1
公开(公告)日：2008-12-25
申请号：US12065202
申请日：2006-08-30
申请人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
发明人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
IPC分类号： G11C17/00 , G11C17/16
CPC分类号： G11C17/16 , G11C17/165 , G11C29/027
摘要： A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at VDD while the bit line drive is switched between VDD and a higher voltage, Vp for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current path for minimal voltage drop during fuse programming. A differential sense amplifier with a programmable reference is used for improved sense margins and can support an entire bit line rather than sense amplifiers being provided for individual fuses.
摘要翻译：一次性可编程只读存储器（OTPROM）在二维阵列中实现，这些阵列具有大规模的自杀可迁移电子保险丝。字线选择通过在VDD处工作的解码逻辑进行，而位线驱动器在VDD和较高电压Vp之间切换，用于编程。因此，OTPROM与其他技术兼容，并且可以与其他技术集成，而无需使用成本加法器，并支持在熔丝编程期间最小化电压降的高电流路径的优化。具有可编程参考的差分读出放大器用于改进的检测余量，并且可以支持整个位线，而不是为各个保险丝提供感测放大器。

99. 发明申请

US20080229144A1 FLEXIBLE ROW REDUNDANCY SYSTEM 失效
标题翻译：灵活的冗余系统
公开(公告)号：US20080229144A1
公开(公告)日：2008-09-18
申请号：US12131307
申请日：2008-06-02
申请人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
发明人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
IPC分类号： G06F11/00
CPC分类号： G11C29/808
摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
摘要翻译：提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。

100. 发明授权

US07286437B2 Three dimensional twisted bitline architecture for multi-port memory 失效
标题翻译：用于多端口存储器的三维扭转位线架构
公开(公告)号：US07286437B2
公开(公告)日：2007-10-23
申请号：US11160302
申请日：2005-06-17
申请人： Hoki Kim , Toshiaki Kirihata
发明人： Hoki Kim , Toshiaki Kirihata
IPC分类号： G11C8/00
CPC分类号： G11C7/18 , G11C5/063 , G11C7/02 , G11C8/16 , G11C11/4097 , G11C11/412 , H01L27/10894 , H01L27/11 , H01L27/1104 , H01L27/11898
摘要： A memory array of dual part cells has a pair of twisted write bitlines and a pair of twisted read bitlines for each column. The twist is made by alternating the vertical position of each bitline pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.
摘要翻译：双部分单元的存储器阵列具有一对扭转写位线和每对列的一对扭转读位线。通过在列的每个部分中交替每个位线对的垂直位置来进行扭转，结果产生共模鼻子并且减小差模噪声。

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