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1. 发明授权

US5745430A Circuit and method to externally adjust internal circuit timing 失效
公开(公告)号：US5745430A
公开(公告)日：1998-04-28
申请号：US777559
申请日：1996-12-30
申请人： Hing Wong , Toshiaki Kirihata , Bozidar Krsnik
发明人： Hing Wong , Toshiaki Kirihata , Bozidar Krsnik
IPC分类号： G06F1/06 , G01R31/30 , G06F1/08 , G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G01R31/3016
摘要： A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The external signal can be applied to an existing pin for chip control, provided that there is no conflict between the test mode and the operation of the integrated circuit.

2. 发明授权

US5903512A Circuit and method to externally adjust internal circuit timing 失效
标题翻译：外部调整内部电路时序的电路和方法
公开(公告)号：US5903512A
公开(公告)日：1999-05-11
申请号：US923593
申请日：1997-09-04
申请人： Hing Wong , Toshiaki Kirihata , Bozidar Krsnik
发明人： Hing Wong , Toshiaki Kirihata , Bozidar Krsnik
IPC分类号： G06F1/06 , G01R31/28 , G01R31/30 , G06F1/08 , G11C7/22 , G11C11/401 , G11C11/407 , G11C29/12 , G11C8/00
CPC分类号： G11C7/22 , G01R31/3016
摘要： A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The external signal can be applied to an existing pin for chip control, provided that there is no conflict between the test mode and the operation of the integrated circuit.
摘要翻译：使用测试模式来使用集成电路中的外部控制来控制内部信号的定时的电路和方法。测试模式被设计为使得内部信号的定时来自外部控制，其可由测试仪任意控制。外部信号可以应用于现有的针脚进行芯片控制，只要测试模式与集成电路的运行没有冲突。

3. 发明授权

US5848008A Floating bitline test mode with digitally controllable bitline equalizers 失效
标题翻译：具有数字可控位线均衡器的浮动位线测试模式
公开(公告)号：US5848008A
公开(公告)日：1998-12-08
申请号：US937528
申请日：1997-09-25
申请人： Toshiaki Kirihata , Hing Wong , Bozidar Krsnik
发明人： Toshiaki Kirihata , Hing Wong , Bozidar Krsnik
IPC分类号： G01R31/28 , G11C11/401 , G11C29/04 , G11C29/50 , G11C29/56 , G11C7/00
CPC分类号： G11C29/50
摘要： A method for generating a floating bitline test mode using digitally controllable bitline equalizers is provided. The method utilizes digitally controlled dummy timing cycles to detect a leaky bitline during the floating bitline test mode. A negative pulsed TEST signal is generated to cause the bitline equalizers to go low and cause the floating bitline state. The implementation of dummy timing cycles eliminates the need for additional external control of internal timings during a bitline test mode. Upon the termination of the dummy timing cycle, the normal read operation continues without interruption.
摘要翻译：提供一种使用数字可控位线均衡器产生浮动位线测试模式的方法。该方法利用数字控制的虚拟定时周期来检测浮动位线测试模式期间的泄漏位线。产生负脉冲+ E，ovs TEST + EE信号，使位线均衡器变为低电平，并导致浮置位线状态。虚拟定时周期的实现消除了在位线测试模式期间对内部定时的额外外部控制的需要。在虚拟定时周期结束时，正常读取操作继续而不中断。

4. 发明授权

US08860433B1 Method and system for self-contained timing and jitter measurement 有权
标题翻译：自适应定时和抖动测量的方法和系统
公开(公告)号：US08860433B1
公开(公告)日：2014-10-14
申请号：US13563529
申请日：2012-07-31
申请人： Victor A. Chang , Bozidar Krsnik
发明人： Victor A. Chang , Bozidar Krsnik
IPC分类号： G01R23/20 , H03D3/24 , G01M1/10
CPC分类号： G01R31/31709
摘要： Disclosed are systems, apparatus, and methods for a self-contained timing and jitter measurement. In various embodiments, a device may include a first clock signal generator operative to provide a first clock signal to a transmitter of a transceiver, where the first clock signal operates at a first frequency. The device may further include a second clock signal generator operative to provide a second clock signal to a receiver of the transceiver, where the second clock signal operates at a second frequency, and where the receiver samples an output of the transmitter at a sampling rate determined by the second frequency. In some embodiments, the device may further include a logic circuit operative to receive an output signal from the receiver and further operative to determine an indication of jitter based on the received output signal.
摘要翻译：公开了用于独立时序和抖动测量的系统，装置和方法。在各种实施例中，设备可以包括第一时钟信号发生器，其操作以向收发器的发射器提供第一时钟信号，其中第一时钟信号以第一频率操作。设备还可以包括第二时钟信号发生器，其操作以向收发器的接收器提供第二时钟信号，其中第二时钟信号以第二频率操作，并且其中接收机以确定的采样率对发射机的输出进行采样按第二个频率。在一些实施例中，设备还可以包括逻辑电路，其可操作以从接收器接收输出信号，并进一步操作以基于所接收的输出信号确定抖动的指示。

5. 发明授权

US07962870B2 Prediction of dynamic current waveform and spectrum in a semiconductor device 有权
标题翻译：预测半导体器件中的动态电流波形和频谱
公开(公告)号：US07962870B2
公开(公告)日：2011-06-14
申请号：US12116095
申请日：2008-05-06
申请人： Peter Boyle , Iliya G. Zamek , Zhe Li , Shishuang Sun , Bozidar Krsnik , James L. Drewniak , Xiaohe Chen , Sandeep Kamalakar Reddy Chandra
发明人： Peter Boyle , Iliya G. Zamek , Zhe Li , Shishuang Sun , Bozidar Krsnik , James L. Drewniak , Xiaohe Chen , Sandeep Kamalakar Reddy Chandra
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H05K1/0231 , H05K3/0005
摘要： A method for determining a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. From the timing characteristics and the power consumption characteristics a time domain current waveform is constructed. The time domain current waveform is then converted to a frequency domain current waveform. With the frequency domain waveform, one skilled in the art can then identify a location and an amount of decoupling capacitors for a printed circuit board housing the circuit design based on the frequency domain current waveform. A computing system configured to perform the method is also provided.
摘要翻译：提供了一种用于确定电路设计的当前频谱的方法。该方法包括确定电路设计的时序特性和功耗特性。从定时特性和功耗特性构建时域电流波形。时域电流波形然后转换为频域电流波形。利用频域波形，本领域技术人员可以基于频域电流波形来识别容纳电路设计的印刷电路板的去耦电容器的位置和量。还提供了被配置为执行该方法的计算系统。

6. 发明申请

US20080288898A1 PREDICTION OF DYNAMIC CURRENT WAVEFORM AND SPECTRUM IN A SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中预测动态电流波形和光谱
公开(公告)号：US20080288898A1
公开(公告)日：2008-11-20
申请号：US12116095
申请日：2008-05-06
申请人： Peter Boyle , Iliya G. Zamek , Zhe Li , Shishuang Sun , Bozidar Krsnik , James L. Drewniak
发明人： Peter Boyle , Iliya G. Zamek , Zhe Li , Shishuang Sun , Bozidar Krsnik , James L. Drewniak
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H05K1/0231 , H05K3/0005
摘要： A method for determining a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. From the timing characteristics and the power consumption characteristics a time domain current waveform is constructed. The time domain current waveform is then converted to a frequency domain current waveform. With the frequency domain waveform, one skilled in the art can then identify a location and an amount of decoupling capacitors for a printed circuit board housing the circuit design based on the frequency domain current waveform. A computing system configured to perform the method is also provided.
摘要翻译：提供了一种用于确定电路设计的当前频谱的方法。该方法包括确定电路设计的时序特性和功耗特性。从定时特性和功耗特性构建时域电流波形。时域电流波形然后转换为频域电流波形。利用频域波形，本领域技术人员可以基于频域电流波形来识别容纳电路设计的印刷电路板的去耦电容器的位置和量。还提供了被配置为执行该方法的计算系统。

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