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91. 发明授权

US06703656B2 Semiconductor memory circuitry including die sites sized for 256M to 275M memory cells in a 12″ wafer 失效
标题翻译：半导体存储器电路包括尺寸为12英寸晶圆中的256M至275M存储单元的模具位置
公开(公告)号：US06703656B2
公开(公告)日：2004-03-09
申请号：US09917844
申请日：2001-07-26
申请人： Brent Keeth , Pierre C. Fazan
发明人： Brent Keeth , Pierre C. Fazan
IPC分类号： H01L2708
CPC分类号： H01L27/105 , H01L27/108 , H01L27/10811 , Y10T29/49121
摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. In accordance with aspects of the invention, considerably greater numbers of die sites per wafer are achieved for 6-inch, 8-inch and 12-inch wafers for 4M, 16M, 64M and 256M integration levels. Further, a semiconductor memory device includes i) a plurality of functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.
摘要翻译：公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。根据本发明的方面，对于用于4M，16M，64M和256M积分级别的6英寸，8英寸和12英寸晶片，实现了相当大数量的每个晶片的晶片位置。此外，半导体存储器件包括：i）布置在形成在半导体管芯上的多个存储器阵列中的多个功能和可操作地寻址的存储器单元; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取，所述存储器阵列中的至少一个包含至少100平方微米的连续管芯表面区域，其具有至少170个功能和可操作地寻址的存储单元。

92. 发明授权

US06696867B2 Voltage generator with stability indicator circuit 失效
标题翻译：电压发生器带稳定指示电路
公开(公告)号：US06696867B2
公开(公告)日：2004-02-24
申请号：US09907565
申请日：2001-07-18
申请人： Brent Keeth , Layne G. Bunker , Scott J. Derner
发明人： Brent Keeth , Layne G. Bunker , Scott J. Derner
IPC分类号： G01R1900
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.
摘要翻译：一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成，阵列被组织成32兆赫阵列阵列，它们被组织成64兆象限。感测放大器位于各个阵列中的相邻行之间，而行解码器位于各个阵列中的相邻列之间。在某些间隙单元中，提供多路复用器以将信号从I / O线传送到数据线。提供了一种数据路径，除了上述之外，还包括阵列I / O块，响应于每个象限的数据，将数据输出到数据读取多路复用器，数据缓冲器和数据驱动器焊盘。写数据路径包括用于向阵列I / O块提供数据的缓冲器和数据写入多路复用器中的数据。提供电源总线，其最小化外部提供的电压的路由，完全环绕每个阵列块，并且在每个阵列块内提供网格化的功率分配。多个电压源提供阵列和外围电路中所需的电压。电源组合以将其功率输出与功率需求相匹配，并保持所需的功率生产能力和去耦电容的比例。提供上电序列电路以控制芯片的上电。提供了冗余的行和列，就像使用操作行和列逻辑地替换有缺陷的行和列所需的电路一样。芯片上还提供电路以支持各种类型的测试模式。

93. 发明授权

US06693836B2 Memory device and method having data path with multiple prefetch I/O configurations 有权
标题翻译：具有多个预取I / O配置的数据路径的存储器件和方法
公开(公告)号：US06693836B2
公开(公告)日：2004-02-17
申请号：US10278528
申请日：2002-10-22
申请人： Brent Keeth , Brian Johnson , Troy A. Manning
发明人： Brent Keeth , Brian Johnson , Troy A. Manning
IPC分类号： G11C700
CPC分类号： G11C7/1072 , G11C7/1006 , G11C7/1018 , G11C7/1027 , G11C7/1045 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C11/4093 , G11C11/4096 , G11C2207/107
摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.
摘要翻译：存储器件可以在高模式或低速模式下操作。在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线终端。在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个巴士总站。

94. 发明授权

US06690609B2 Memory device and method having data path with multiple prefetch I/O configurations 有权
标题翻译：具有多个预取I / O配置的数据路径的存储器件和方法
公开(公告)号：US06690609B2
公开(公告)日：2004-02-10
申请号：US10278529
申请日：2002-10-22
申请人： Brent Keeth , Brian Johnson , Troy A. Manning
发明人： Brent Keeth , Brian Johnson , Troy A. Manning
IPC分类号： G11C700
CPC分类号： G11C7/1072 , G11C7/1006 , G11C7/1018 , G11C7/1027 , G11C7/1045 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C11/4093 , G11C11/4096 , G11C2207/107
摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.
摘要翻译：存储器件可以在高模式或低速模式下操作。在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线终端。在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个巴士总站。

95. 发明授权

US06687185B1 Method and apparatus for setting and compensating read latency in a high speed DRAM 有权
标题翻译：用于设置和补偿高速DRAM中读取延迟的方法和装置
公开(公告)号：US06687185B1
公开(公告)日：2004-02-03
申请号：US10230221
申请日：2002-08-29
申请人： Brent Keeth , Brian Johnson , Feng Lin
发明人： Brent Keeth , Brian Johnson , Feng Lin
IPC分类号： G11C800
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1066 , G11C11/4076 , G11C2207/2281
摘要： An apparatus and method for coordinating the variable timing of internal clock signals derived from an external clock signal to ensure that read data and a read clock used to latch the read data arrive at the data latch in synchronism and with a specified read latency. A read clock is produced from the external clock signal in a delay lock loop circuit and a start signal, produced in response to a read command, is passed through a delay circuit slaved with the delay lock loop so that the read clock signal and a delayed start signal are subject to the same internal timing variations. The delayed start signal is used to thereby control the output of read data by the read clock signal.
摘要翻译：一种用于协调从外部时钟信号导出的内部时钟信号的可变定时的装置和方法，以确保读取数据和用于锁存读取数据的读取时钟同步并以指定的读取延迟到达数据锁存器。在延迟锁定环路电路中，从外部时钟信号产生读时钟，并且响应于读命令产生的起始信号通过与延迟锁定环相对应的延迟电路，使得读时钟信号和延迟启动信号受到相同的内部时序变化。延迟启动信号用于通过读时钟信号控制读数据的输出。

96. 发明授权

US06674378B2 Predictive timing calibration for memory devices 有权
标题翻译：存储器件的预测定时校准
公开(公告)号：US06674378B2
公开(公告)日：2004-01-06
申请号：US10365399
申请日：2003-02-13
申请人： Brian Johnson , Brent Keeth
发明人： Brian Johnson , Brent Keeth
IPC分类号： H03M110
CPC分类号： G11C11/4076 , G11C7/1072 , G11C2207/2254
摘要： The present invention provides a unique way of using a 2N bit synchronization pattern to obtain a faster and more reliable calibration of multiple data paths in a memory system. If the 2N bit synchronization pattern is generated with a known clock phase relationship, then the data-to-clock phase alignment can be determined using simple decode logic to predict the next m-bits from a just-detected m-bits. If the succeeding m-bit pattern does not match the predicted pattern, then the current data-to-clock alignment fails for a particular delay value adjustment in the data path undergoing alignment, and the delay in that data path is adjusted to a new value. The invention also ensures that data alignment will occur to a desired edge of the clock signal, e.g., a positive going edge, by forcing a failure of all predicted m-bit patterns which are associated with an undesired edge, e.g., a negative going edge, of the clock signal.
摘要翻译：本发明提供使用2＆lt; N＆gt;位同步模式以获得存储器系统中的多个数据路径的更快更可靠的校准的独特方式。如果以已知的时钟相位关系产生2 位同步模式，则可以使用简单的解码逻辑来确定数据到时钟相位对准，以便从刚刚检测到的m位来预测下一个m位。如果后续的m位模式与预测模式不匹配，则对于经历对准的数据路径中的特定延迟值调整，当前数据对时钟对准失败，并且该数据路径中的延迟被调整到新值。本发明还确保通过强制与不期望的边缘相关联的所有预测的m位模式的故障（例如，正向沿），时钟信号的期望边缘（例如，正向边缘）将发生数据对准的时钟信号。

97. 发明授权

US06674310B1 256 Meg dynamic random access memory 失效
公开(公告)号：US06674310B1
公开(公告)日：2004-01-06
申请号：US09930344
申请日：2001-08-15
申请人： Brent Keeth , Layne G. Bunker , Scott J. Derner
发明人： Brent Keeth , Layne G. Bunker , Scott J. Derner
IPC分类号： G01R1900
CPC分类号： G11C11/4076 , G11C11/4074 , G11C11/4097 , H01L27/10805
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

98. 发明授权

US06662304B2 Method and apparatus for bit-to-bit timing correction of a high speed memory bus 有权
公开(公告)号：US06662304B2
公开(公告)日：2003-12-09
申请号：US10046944
申请日：2002-01-14
申请人： Brent Keeth , Terry R. Lee , Kevin Ryan , Troy A. Manning
发明人： Brent Keeth , Terry R. Lee , Kevin Ryan , Troy A. Manning
IPC分类号： G06F112
CPC分类号： G06F5/06 , G06F2205/102
摘要： A synchronization circuit performs bit-to-bit timing correction of respective digital signals in digital signal packets applied to a packetized memory device. Each digital signal packet includes a plurality of digital signals applied to respective latches in the packetized memory device. A clock generator circuit generates a plurality of internal clock signals responsive to the external clock signal, each internal clock signal having a corresponding phase relative to the external clock signal. A plurality of selection circuits are coupled to the clock generator circuit and each has an output coupled to a clock terminal of an associated latch. Each selection circuit applies one of the internal clock signals to clock the associated latch in response to a phase command signal. An evaluation circuit receives digital signals sequentially stored in a selected one of the latches and generates a results signal indicating whether each of the digital signals has an expected value. A control circuit sequentially selects the latches and operates for each selected latch to adjust the phase command signals applied to the selection circuit coupled to the selected latch and store respective results signals sequentially received from the evaluation circuit for each phase command signal. The control circuit generates a final phase command signal from the stored results signals and applies each final phase command signal to the corresponding selection circuit Each of the final phase command signals adjusts the phase of clock signal applied to the associated latch relative to the digital signal applied to the latch so that the digital signal is successfully captured responsive to the clock signal.

99. 发明授权

US06600671B2 Reduced area sense amplifier isolation layout in a dynamic RAM architecture 失效
公开(公告)号：US06600671B2
公开(公告)日：2003-07-29
申请号：US10225908
申请日：2002-08-21
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： G11C502
CPC分类号： G11C7/18 , G11C7/065 , G11C11/4091
摘要： A memory device has an array of memory cells which are positioned in a first block and a second block. The memory cells are arranged in rows and columns. A plurality of bit lines is coupled to the memory cells and a plurality of word lines is coupled to the memory cells. A sense amplifier is positioned between the first block and the second block, and a plurality of electrical connections is made between the sense amplifier and the bit lines. A plurality of isolation transistors are electrically connected in series with the electrical connections, the isolation transistors being located within the first and second blocks and spaced from the sense amplifier block.

100. 发明授权

US06594168B2 256 Meg dynamic random access memory 失效
公开(公告)号：US06594168B2
公开(公告)日：2003-07-15
申请号：US09880747
申请日：2001-06-13
申请人： Brent Keeth , Layne G. Bunker
发明人： Brent Keeth , Layne G. Bunker
IPC分类号： G11C502
CPC分类号： H01L27/10805 , G11C5/025 , G11C5/063
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

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