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91. 发明申请

US20080194095A1 UNDERCUT-FREE BLM PROCESS FOR PB-FREE AND PB-REDUCED C4 有权
标题翻译：无铅和PB减少C4的无底板BLM工艺
公开(公告)号：US20080194095A1
公开(公告)日：2008-08-14
申请号：US11673618
申请日：2007-02-12
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
IPC分类号： H01L21/44
CPC分类号： H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/03462 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05006 , H01L2224/0501 , H01L2224/05083 , H01L2224/05546 , H01L2224/05624 , H01L2224/114 , H01L2224/11462 , H01L2224/1147 , H01L2224/11472 , H01L2224/11474 , H01L2224/116 , H01L2224/11849 , H01L2224/11902 , H01L2224/13006 , H01L2224/13023 , H01L2224/1308 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/16 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/00014 , H01L2224/13099
摘要： A system and method for eliminating undercut when forming a C4 solder bump for BLM (Ball Limiting Metallurgy) and improving the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP with a bottom conductive layer of the barrier metal stack removed by etching. The diffusion barrier and C4 solder bump may be formed by electroless plating, in one embodiment, using a maskless technique, or by an electroplating techniques using a patterned mask. This allows the pitch of the C4 solder bumps to be reduced.
摘要翻译：一种用于在形成用于BLM（限流冶金）的C4焊料凸块并提高C4间距时消除底切的系统和方法。在该过程中，在金属焊盘层上方沉积阻挡层金属堆叠。通过CMP对阻挡层金属（例如Cu）的顶层进行图案化，通过蚀刻去除阻挡金属叠层的底部导电层。扩散阻挡层和C4焊料凸点可以通过化学镀来形成，在一个实施例中，使用无掩模技术，或通过使用图案化掩模的电镀技术形成。这样可以减少C4焊料凸点的间距。

92. 发明申请

US20080057677A1 CHIP LOCATION IDENTIFICATION 审中-公开
标题翻译：芯片位置识别
公开(公告)号：US20080057677A1
公开(公告)日：2008-03-06
申请号：US11470355
申请日：2006-09-06
申请人： Sylvie Charles , Timothy H. Daubenspeck , Jeffrey P. Gambino , Robert Hannon , Ian D. Melville , Christopher D. Muzzy , Wolfgang Sauter
发明人： Sylvie Charles , Timothy H. Daubenspeck , Jeffrey P. Gambino , Robert Hannon , Ian D. Melville , Christopher D. Muzzy , Wolfgang Sauter
IPC分类号： H01L21/78 , H01L23/544
CPC分类号： H01L23/544 , H01L24/16 , H01L2223/5442 , H01L2223/54433 , H01L2223/5444 , H01L2223/54473 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/16 , H01L2224/83102 , H01L2224/92125 , H01L2924/00014 , H01L2924/14 , H01L2924/15184 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Chip location identification using dummy solder bead(s) is disclosed. A structure may include an integrated circuit (IC) chip including a plurality of solder beads for electrically coupling the IC chip to other structure, and a chip location identifier including at least one dummy solder bead on the IC chip, the chip location identifier representing a unique location of the IC chip in a wafer prior to dicing. The structure allows location tracking of an IC chip within a wafer without any additional processing, space, or mask levels. The structure can also be evaluated (visually or electrically) at the packaging level.
摘要翻译：公开了使用虚拟焊珠的芯片位置识别。结构可以包括集成电路（IC）芯片，其包括用于将IC芯片电耦合到其他结构的多个焊料珠，以及包括IC芯片上的至少一个虚拟焊珠的芯片位置标识符，芯片位置标识符表示 IC芯片在切割之前在晶片中的独特位置。该结构允许在晶片内的IC芯片的位置跟踪，而没有任何额外的处理，空间或掩模级别。还可以在包装层面评估（视觉或电气）结构。

93. 发明授权

US07176583B2 Damascene patterning of barrier layer metal for C4 solder bumps 失效
标题翻译：用于C4焊锡凸块的阻挡层金属的镶嵌图案
公开(公告)号：US07176583B2
公开(公告)日：2007-02-13
申请号：US10710562
申请日：2004-07-21
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
IPC分类号： H01L23/52 , H01L23/48 , H01L23/40 , H01L23/485 , H01L23/498
CPC分类号： H01L24/12 , B23K3/0623 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05006 , H01L2224/05017 , H01L2224/05546 , H01L2224/05556 , H01L2224/05557 , H01L2224/05599 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/13006 , H01L2224/131 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , Y10T29/49144 , H01L2224/13099
摘要： A system and method for forming a novel C4 solder bump for BLM (Ball Limiting Metallurgy) includes a novel damascene technique is implemented to eliminate the Cu undercut problem and improve the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP. Only bottom layers of the barrier metal stack are patterned by a wet etching. The wet etch time for the Cu-based metals is greatly reduced resulting in a reduced undercut. This allows the pitch of the C4 solder bumps to be reduced. An alternate method includes use of multiple vias at the solder bump terminal.
摘要翻译：用于形成用于BLM（Ball Limite Metallurgy）的新型C 4焊料凸块的系统和方法包括实现新颖的镶嵌技术以消除Cu底切问题并提高C 4间距。在该过程中，在金属焊盘层上方沉积阻挡层金属堆叠。通过CMP对阻挡层金属（例如Cu）的顶层进行图案化。仅通过湿蚀刻图案化阻挡金属叠层的底层。 Cu基金属的湿蚀刻时间大大降低，从而减少了底切。这样可以减小C 4焊料凸点的间距。一种替代方法包括在焊料凸点端子处使用多个通孔。

94. 发明授权

US06833720B1 Electrical detection of dicing damage 失效
标题翻译：电检检测切片损坏
公开(公告)号：US06833720B1
公开(公告)日：2004-12-21
申请号：US10604572
申请日：2003-07-31
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Thomas L. McDevitt , Anthony K. Stamper
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： G01R3102
CPC分类号： H01L22/34 , G01N27/205 , G01R31/2851 , G01R31/2896 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： Electrical detection is provided for dicing damage to moisture barrier/edge seals of IC chips which include a low-K dielectric material, a moisture barrier/edge seal for the IC chip, and a moisture damage sensor circuit positioned on the IC chip in proximity to the moisture barrier/edge seal. One or a plurality of moisture barrier/edge seals can be positioned along peripheral edges of the IC chip, and one or more moisture damage sensor circuit(s) can be positioned between the plurality of moisture barrier/edge seal(s), or between an active area of the IC chip and the moisture barrier/edge seal(s), or on a peripheral area of the IC chip outside of the moisture barrier/edge seal(s). The sensor circuit can comprises a single or a plurality of, via chain(s) including a plurality of vias connected in series, or wire monitor circuit(s) extending in a serpentine conductive path through a plurality of wiring levels and vias, or interconnect(s), and the system can monitor the resistance(s) or leakage(s) or ratio(s) of parameters of the sensor circuit(s).
摘要翻译：提供电检测，用于对包括低K介电材料，IC芯片的防潮/边缘密封以及位于IC芯片附近的水分损伤传感器电路的IC芯片的防潮/边缘密封的切割损伤防潮/边缘密封。一个或多个防潮/边缘密封件可以沿着IC芯片的周边边缘定位，并且一个或多个水分损伤传感器电路可以位于多个防潮层/边缘密封件之间，或者位于 IC芯片的有源区域和防潮/边缘密封件，或在防潮层/边缘密封件外部的IC芯片的周边区域上。传感器电路可以包括单个或多个通孔链，其包括串联连接的多个通孔，或者通过多个布线层和通孔在蛇形导电路径中延伸的线监视器电路，或互连并且系统可以监测传感器电路的参数的电阻或泄漏或比率。

95. 发明授权

US08298917B2 Process for wet singulation using a dicing singulation structure 有权
标题翻译：使用切割分离结构进行湿分离的方法
公开(公告)号：US08298917B2
公开(公告)日：2012-10-30
申请号：US12423254
申请日：2009-04-14
申请人： Paul S. Andry , Timothy H. Daubenspeck , Jeffrey P. Gambino , Edmund J. Sprogis , Cornelia K. Tsang
发明人： Paul S. Andry , Timothy H. Daubenspeck , Jeffrey P. Gambino , Edmund J. Sprogis , Cornelia K. Tsang
IPC分类号： H01L23/544
CPC分类号： H01L21/78
摘要： A method includes receiving at least one wafer having a front side and a backside, where the front side has a plurality of integrated circuit chips thereon. The backside of the wafer is thinned, a pattern of material is removed from the backside of the wafer to form a plurality of dicing trenches. Each of the dicing trenches are positioned opposite a location on the front side of the wafer that corresponds to edges of each of the plurality of chips. The dicing trenches are filled with a filler material and a dicing support is attached to a front side of the wafer. The filler material is removed from the dicing trenches, and a force is applied to the dicing support to separate each of the plurality of chips on the wafer from each other along the dicing trenches.
摘要翻译：一种方法包括接收具有前侧和后侧的至少一个晶片，其中前侧在其上具有多个集成电路芯片。晶片的背面变薄，从晶片的背面去除材料图案以形成多个切割沟槽。每个切割槽位于对应于多个芯片中的每一个的边缘的晶片正面的位置。切割槽填充有填充材料，并且切割支撑件附接到晶片的前侧。从切割槽移除填充材料，并且将力施加到切割支撑件，以将晶片上的多个芯片中的每一个沿着切割沟槽彼此分离。

96. 发明申请

US20120261813A1 REINFORCED VIA FARM INTERCONNECT STRUCTURE, A METHOD OF FORMING A REINFORCED VIA FARM INTERCONNECT STRUCTURE AND A METHOD OF REDESIGNING AN INTEGRATED CIRCUIT CHIP TO INCLUDE SUCH A REINFORCED VIA FARM INTERCONNECT STRUCTURE 审中-公开
标题翻译：通过农业互连结构增强，通过农业互连结构形成增强的方法以及重新组合集成电路芯片以包括通过农业互连结构增强的方法
公开(公告)号：US20120261813A1
公开(公告)日：2012-10-18
申请号：US13087449
申请日：2011-04-15
申请人： Felix P. Anderson , Timothy H. Daubenspeck , Jeffrey P. Gambino , Donald R. Letourneau , Thomas L. McDevitt
发明人： Felix P. Anderson , Timothy H. Daubenspeck , Jeffrey P. Gambino , Donald R. Letourneau , Thomas L. McDevitt
IPC分类号： H01L23/498 , G06F11/22 , H01L21/60
CPC分类号： H01L24/11 , H01L23/522 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05096 , H01L2224/05147 , H01L2224/05569 , H01L2224/05571 , H01L2224/13022 , H01L2224/131 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2224/05552 , H01L2224/81805
摘要： Disclosed is reinforced via farm interconnect structure for an integrated circuit chip that minimizes delamination caused by tensile stresses applied to the chip through lead-free C4 connections during thermal cycling. The reinforced via farm interconnect structure includes a plurality of vias electrically connecting metal wires within different wiring levels and, for reinforcement, further incorporates dielectric columns into the lower metal wire so that the areas around the metal-to-metal interface between the vias and the lower metal wire contain a relatively strong dielectric-to-dielectric interface. The reinforced via farm interconnect structure can be located in an area of the chip at risk for delamination and, for added strength, can have a reduced via density relative to conventional via farm interconnect structures located elsewhere on the chip. Also disclosed are a method of forming the reinforced via farm interconnect structure and a method of redesigning an integrated circuit chip to include reinforced via farm interconnect structure(s).
摘要翻译：公开了通过用于集成电路芯片的农场互连结构来加强，其最小化在热循环期间通过无铅C4连接施加到芯片的拉伸应力引起的分层。增强通孔农场互连结构包括多个通孔，电连接不同布线层内的金属线，并且为了加强，进一步将电介质柱并入下金属线，使得通孔和通孔之间的金属到金属界面周围的区域下部金属线包含相当强的电介质至电介质界面。增强的通孔农场互连结构可以位于芯片的具有分层风险的区域中，并且为了增加的强度，可以相对于位于芯片上其他地方的常规通孔农场互连结构，具有降低的通孔密度。还公开了一种形成加强的通孔农场互连结构的方法和重新设计集成电路芯片以包括增强的农场互连结构的方法。

97. 发明授权

US06734047B1 Thinning of fuse passivation after C4 formation 有权
标题翻译： C4形成后保险丝钝化的变薄
公开(公告)号：US06734047B1
公开(公告)日：2004-05-11
申请号：US10065884
申请日：2002-11-27
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , William T. Motsiff
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , William T. Motsiff
IPC分类号： H01L2182
CPC分类号： H01L23/5258 , H01L2224/05001 , H01L2224/05022 , H01L2224/05026 , H01L2224/05027 , H01L2224/05184 , H01L2224/05572 , H01L2224/056 , H01L2224/11 , H01L2924/0002 , H01L2924/00 , H01L2924/00014 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166
摘要： A method of forming a fuse structure in which passivating material over the fuse has a controlled, substantially uniform thickness that is provided after C4 metallurgy formation. A laser fuse deletion process for the fuse formed by this method is also disclosed.
摘要翻译：形成保险丝结构的方法，其中在熔断器上方的钝化材料具有在C4冶金形成之后提供的受控的，基本均匀的厚度。还公开了通过该方法形成的保险丝的激光熔丝删除处理。

98. 发明授权

US08921975B2 System and method for forming aluminum fuse for compatibility with copper BEOL interconnect scheme 有权
标题翻译：用于形成铝保险丝的系统和方法，用于与铜BEOL互连方案兼容
公开(公告)号：US08921975B2
公开(公告)日：2014-12-30
申请号：US13488870
申请日：2012-06-05
申请人： Felix P. Anderson , Timothy H. Daubenspeck , Jeffrey P. Gambino , Timothy S. Hayes , Donald R. Letourneau , Thomas L. McDevitt , Anthony K. Stamper
发明人： Felix P. Anderson , Timothy H. Daubenspeck , Jeffrey P. Gambino , Timothy S. Hayes , Donald R. Letourneau , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： H01L21/768 , H01L23/525
CPC分类号： H01L21/76892 , H01L21/76838 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.
摘要翻译：一种半导体熔丝器件和一种制造熔丝器件的方法，该熔丝器件包括最后的金属互连层，其包括至少两个分立的金属导体，沉积在最后的金属互连层和至少两个分立的金属导体上的层间电介质层，连接至少两个分立的金属导体的线铝保险丝，以及铝保险丝上方的保险丝开口。

99. 发明授权

US08710656B2 Redistribution layer (RDL) with variable offset bumps 有权
标题翻译：具有可变偏移凸块的再分配层（RDL）
公开(公告)号：US08710656B2
公开(公告)日：2014-04-29
申请号：US13553882
申请日：2012-07-20
申请人： Timothy H. Daubenspeck , Brian M. Erwin , Jeffrey P. Gambino , Wolfgang Sauter , George J. Scott
发明人： Timothy H. Daubenspeck , Brian M. Erwin , Jeffrey P. Gambino , Wolfgang Sauter , George J. Scott
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L23/3192 , H01L23/525 , H01L23/562 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L2224/02375 , H01L2224/02377 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05093 , H01L2224/05124 , H01L2224/05147 , H01L2224/05569 , H01L2224/05572 , H01L2224/0603 , H01L2224/0614 , H01L2224/1146 , H01L2224/1147 , H01L2224/13027 , H01L2224/131 , H01L2224/14104 , H01L2224/14131 , H01L2924/00014 , H01L2924/3512 , H01L2924/00012 , H01L2924/014 , H01L2224/05552
摘要： An integrated circuit (IC) chip is disclosed including a plurality of metal vertical interconnect accesses (vias) in a back end of line (BEOL) layer, a redistribution layer (RDL) on the BEOL layer, the BEOL layer having a plurality of bond pads, each bond pad connected to at least one corresponding metal via through the RDL; and a solder bump connected to each bond pad, wherein each solder bump is laterally offset from the corresponding metal via connected to the bond pad towards a center of the IC chip by an offset distance, wherein the offset distance is non-uniform across the IC chip. In one embodiment, the offset distance for each solder bump is proportionate to a distance between the center of the IC chip and the center of the corresponding solder bump pad structure for that solder bump.
摘要翻译：公开了一种集成电路（IC）芯片，其包括在后端（BEOL）层中的多个金属垂直互连访问（通孔），BEOL层上的再分配层（RDL），BEOL层具有多个键焊盘，每个接合焊盘通过RDL连接到至少一个对应的金属通孔; 以及连接到每个接合焊盘的焊料凸块，其中每个焊料凸块横向偏离连接到所述接合焊盘的相应金属通孔朝向所述IC芯片的中心偏移距离，其中所述偏移距离在所述IC 芯片。在一个实施例中，每个焊料凸块的偏移距离与IC芯片的中心与该焊料凸块的相应焊料凸块焊盘结构的中心之间的距离成比例。

100. 发明授权

US08212357B2 Combination via and pad structure for improved solder bump electromigration characteristics 有权
标题翻译：组合通孔和焊盘结构，用于改善焊料凸块电迁移特性
公开(公告)号：US08212357B2
公开(公告)日：2012-07-03
申请号：US12188235
申请日：2008-08-08
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Timothy D. Sullivan
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Timothy D. Sullivan
IPC分类号： H01L23/488 , H01L21/44
CPC分类号： H01L24/11 , H01L23/5226 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/05022 , H01L2224/13028 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2924/0001 , H01L2924/01005 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433
摘要： The invention generally relates to semiconductor devices, and more particularly to structures and methods for enhancing electromigration (EM) performance in solder bumps and related structures. A semiconductor structure includes a wire comprising first and second wire segments, a pad formed over the wire, and a ball limiting metallization (BLM) layer formed over the pad. The semiconductor structure also includes a solder bump formed over the BLM layer, a terminal via formed over the BLM layer, and at least one peripheral via formed between the second wire segment and the pad. The first and second wire segments are discrete wire segments.
摘要翻译：本发明一般涉及半导体器件，更具体地涉及用于增强焊料凸点和相关结构中的电迁移（EM）性能的结构和方法。半导体结构包括包括第一和第二线段的线，在线上形成的焊盘以及形成在焊盘上的球限制金属化（BLM）层。半导体结构还包括形成在BLM层上的焊料凸块，在BLM层上形成的端子通孔，以及形成在第二线段和焊盘之间的至少一个外围通孔。第一和第二线段是分立的线段。

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