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1. 发明授权

US06833720B1 Electrical detection of dicing damage 失效
标题翻译：电检检测切片损坏
公开(公告)号：US06833720B1
公开(公告)日：2004-12-21
申请号：US10604572
申请日：2003-07-31
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Thomas L. McDevitt , Anthony K. Stamper
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： G01R3102
CPC分类号： H01L22/34 , G01N27/205 , G01R31/2851 , G01R31/2896 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： Electrical detection is provided for dicing damage to moisture barrier/edge seals of IC chips which include a low-K dielectric material, a moisture barrier/edge seal for the IC chip, and a moisture damage sensor circuit positioned on the IC chip in proximity to the moisture barrier/edge seal. One or a plurality of moisture barrier/edge seals can be positioned along peripheral edges of the IC chip, and one or more moisture damage sensor circuit(s) can be positioned between the plurality of moisture barrier/edge seal(s), or between an active area of the IC chip and the moisture barrier/edge seal(s), or on a peripheral area of the IC chip outside of the moisture barrier/edge seal(s). The sensor circuit can comprises a single or a plurality of, via chain(s) including a plurality of vias connected in series, or wire monitor circuit(s) extending in a serpentine conductive path through a plurality of wiring levels and vias, or interconnect(s), and the system can monitor the resistance(s) or leakage(s) or ratio(s) of parameters of the sensor circuit(s).
摘要翻译：提供电检测，用于对包括低K介电材料，IC芯片的防潮/边缘密封以及位于IC芯片附近的水分损伤传感器电路的IC芯片的防潮/边缘密封的切割损伤防潮/边缘密封。一个或多个防潮/边缘密封件可以沿着IC芯片的周边边缘定位，并且一个或多个水分损伤传感器电路可以位于多个防潮层/边缘密封件之间，或者位于 IC芯片的有源区域和防潮/边缘密封件，或在防潮层/边缘密封件外部的IC芯片的周边区域上。传感器电路可以包括单个或多个通孔链，其包括串联连接的多个通孔，或者通过多个布线层和通孔在蛇形导电路径中延伸的线监视器电路，或互连并且系统可以监测传感器电路的参数的电阻或泄漏或比率。

2. 发明授权

US08921975B2 System and method for forming aluminum fuse for compatibility with copper BEOL interconnect scheme 有权
标题翻译：用于形成铝保险丝的系统和方法，用于与铜BEOL互连方案兼容
公开(公告)号：US08921975B2
公开(公告)日：2014-12-30
申请号：US13488870
申请日：2012-06-05
申请人： Felix P. Anderson , Timothy H. Daubenspeck , Jeffrey P. Gambino , Timothy S. Hayes , Donald R. Letourneau , Thomas L. McDevitt , Anthony K. Stamper
发明人： Felix P. Anderson , Timothy H. Daubenspeck , Jeffrey P. Gambino , Timothy S. Hayes , Donald R. Letourneau , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： H01L21/768 , H01L23/525
CPC分类号： H01L21/76892 , H01L21/76838 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.
摘要翻译：一种半导体熔丝器件和一种制造熔丝器件的方法，该熔丝器件包括最后的金属互连层，其包括至少两个分立的金属导体，沉积在最后的金属互连层和至少两个分立的金属导体上的层间电介质层，连接至少两个分立的金属导体的线铝保险丝，以及铝保险丝上方的保险丝开口。

3. 发明申请

US20130320488A1 SYSTEM AND METHOD FOR FORMING ALUMINUM FUSE FOR COMPATIBILITY WITH COPPER BEOL INTERCONNECT SCHEME 有权
标题翻译：用于形成铝熔丝的系统和方法与铜球互连方案的兼容性
公开(公告)号：US20130320488A1
公开(公告)日：2013-12-05
申请号：US13488870
申请日：2012-06-05
申请人： Felix P. Anderson , Timothy H. Daubenspeck , Jeffrey P. Gambino , Timothy S. Hayes , Donald R. Letourneau , Thomas L. McDevitt , Anthony K. Stamper
发明人： Felix P. Anderson , Timothy H. Daubenspeck , Jeffrey P. Gambino , Timothy S. Hayes , Donald R. Letourneau , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L21/76892 , H01L21/76838 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.
摘要翻译：一种半导体熔丝器件和一种制造熔丝器件的方法，该熔丝器件包括最后的金属互连层，其包括至少两个分立的金属导体，沉积在最后的金属互连层和至少两个分立的金属导体上的层间电介质层，连接至少两个分立的金属导体的线铝保险丝，以及铝保险丝上方的保险丝开口。

4. 发明授权

US06991971B2 Method for fabricating a triple damascene fuse 失效
标题翻译：三镶嵌保险丝的制造方法
公开(公告)号：US06991971B2
公开(公告)日：2006-01-31
申请号：US10675177
申请日：2003-09-30
申请人： Timothy H. Daubenspeck , Thomas L. McDevitt , William T. Motsiff , Anthony K. Stamper
发明人： Timothy H. Daubenspeck , Thomas L. McDevitt , William T. Motsiff , Anthony K. Stamper
IPC分类号： H01L21/82
CPC分类号： H01L23/53295 , H01L23/5256 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a fuse for a semiconductor device. The method including: providing a substrate; forming a first dielectric layer on a top surface of said substrate; forming a dielectric mandrel on a top surface of said first dielectric layer; forming a second dielectric layer on top of said mandrel and a top surface of said first dielectric layer forming contact openings down to said substrate in said first and second dielectric layers on opposite sides of said mandrel, said contacts spaced away from said mandrel and leaving portions of said second dielectric layer between said mandrel and said contacts; removing said second dielectric layer from over said mandrel between said contact openings to form a trough; and filling said trough and contact openings with a conductor.
摘要翻译：一种制造用于半导体器件的熔丝的方法。该方法包括：提供衬底; 在所述衬底的顶表面上形成第一电介质层; 在所述第一介电层的顶表面上形成介电心轴; 在所述心轴的顶部上形成第二电介质层，并且所述第一电介质层的顶表面在所述心轴的相对侧上的所述第一和第二介电层中向下形成接触开口，所述触头与所述心轴间隔开并留下部分所述第二电介质层位于所述心轴和所述触头之间; 从所述心轴上的所述接触开口之间移除所述第二电介质层以形成槽; 并用导体填充所述槽和接触开口。

5. 发明授权

US06667533B2 Triple damascene fuse 失效
公开(公告)号：US06667533B2
公开(公告)日：2003-12-23
申请号：US09684000
申请日：2002-03-11
申请人： Timothy H. Daubenspeck , Thomas L. McDevitt , William T. Motsiff , Anthony K. Stamper
发明人： Timothy H. Daubenspeck , Thomas L. McDevitt , William T. Motsiff , Anthony K. Stamper
IPC分类号： H01L2900
CPC分类号： H01L23/53295 , H01L23/5256 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a conductive fuse for a semiconductor device, comprising: a pair of contact portions integrally connected to a fusible portion by connecting portions; the contact portions thicker than the connecting portions and the connecting portions thicker than the fusible portion; a first dielectric under the connecting portions and the fusible portion and extending between the pair of contact portions; and a second dielectric between the first dielectric and the fusible portion, the second dielectric extending between the connecting portions and defining the length of the fusible portion.

6. 发明申请

US20080146040A1 LOCAL PLASMA PROCESSING 审中-公开
标题翻译：本地等离子体处理
公开(公告)号：US20080146040A1
公开(公告)日：2008-06-19
申请号：US12041782
申请日：2008-03-04
申请人： Jeffrey P. Gambino , Thomas L. McDevitt , Anthony K. Stamper
发明人： Jeffrey P. Gambino , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： H01L21/31
CPC分类号： C23C16/04 , C23C16/513 , H01J37/32366
摘要： A method and an apparatus for performing the method. The method includes: (a) providing an apparatus, wherein the apparatus comprises (i) a chamber, (ii) a plasma device being in and coupled to the chamber, (iii) a shower head being in and coupled to the chamber, and (iv) a chuck being in and coupled to the chamber; (b) placing the substrate on the chuck; (c) using the plasma device to receive a plasma device gas and generate a plasma; (d) directing the plasma at a pre-specified area on the substrate; and (e) using the shower head to receive and distribute a shower head gas in the chamber, wherein the plasma device gas and the shower head gas are selected such that the plasma and the shower head gas when mixed with each other result in a chemical reaction that forms a film at the pre-specified area on the substrate.
摘要翻译：一种用于执行该方法的方法和装置。该方法包括：（a）提供一种设备，其中所述设备包括（i）室，（ii）位于室中并耦合到所述室的等离子体设备，（iii）淋浴喷头位于并联接到所述室，以及（iv）卡盘位于并联接到所述腔室; （b）将基板放置在卡盘上; （c）使用等离子体装置接收等离子体装置气体并产生等离子体; （d）将等离子体引导到基板上的预定区域; 以及（e）使用所述淋浴头来接收和分配所述腔室中的淋浴头气体，其中所述等离子体装置气体和所述喷淋头气体被选择为使得当彼此混合时所述等离子体和所述淋浴头气体产生化学物质在基板上的预定区域形成膜的反应。

7. 发明授权

US07015150B2 Exposed pore sealing post patterning 失效
标题翻译：曝露孔密封柱图案化
公开(公告)号：US07015150B2
公开(公告)日：2006-03-21
申请号：US10709747
申请日：2004-05-26
申请人： Edward C. Cooney, III , John A. Fitzsimmons , Jeffrey P. Gambino , Stephen E. Luce , Thomas L. McDevitt , Lee M. Nicholson , Anthony K. Stamper
发明人： Edward C. Cooney, III , John A. Fitzsimmons , Jeffrey P. Gambino , Stephen E. Luce , Thomas L. McDevitt , Lee M. Nicholson , Anthony K. Stamper
IPC分类号： H01L21/31 , H01L21/302
CPC分类号： H01L21/76831 , H01L21/02107 , H01L21/02203 , H01L21/02337 , H01L21/0234 , H01L21/02362 , H01L21/3105 , H01L21/31116 , H01L21/31695 , H01L21/76802 , H01L21/76807 , H01L21/76826 , H01L21/76843 , H01L21/76844 , H01L21/76868
摘要： Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.
摘要翻译：具有闭孔层的方法和结构，用于封闭图案化的多孔低k电介质层中的暴露孔，以及可选地在低k电介质上的反应性衬垫。第一反应物被吸收或保留在图案化介电层中的暴露孔中，然后将第二反应物引入开口中，使得其进入暴露的孔，同时第一反应物分子同时脱气。第二反应物与暴露孔的口部区域处的脱气的第一反应物分子原位反应，以形成穿过暴露孔的口部区域的孔闭合层，同时保留每个孔隙的一部分以保持其孔的特性和性质多孔低k电介质层。任选地，第一反应物可以被吸附到低k电介质上，使得当将第二反应物引入图案化的电介质开口中时，还在低k电介质上形成反应性衬垫。

8. 发明申请

US20100052172A1 METHOD OF FABRICATING COPPER DAMASCENE AND DUAL DAMASCENE INTERCONNECT WIRING 有权
标题翻译：铜复合材料和双组分互连线的制备方法
公开(公告)号：US20100052172A1
公开(公告)日：2010-03-04
申请号：US12614861
申请日：2009-11-09
申请人： Jeffrey P. Gambino , William Hill , Kenneth E. McAvey, JR. , Thomas L. McDevitt , Anthony K. Stamper , Arthur C. Winslow , Robert Zwonik
发明人： Jeffrey P. Gambino , William Hill , Kenneth E. McAvey, JR. , Thomas L. McDevitt , Anthony K. Stamper , Arthur C. Winslow , Robert Zwonik
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L21/76832 , H01L21/76802 , H01L21/76807 , H01L21/76834
摘要： An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.
摘要翻译：一种集成电路和集成电路的制造方法，所述方法包括：（a）提供衬底; （b）在所述基板上形成铜扩散阻挡层; （c）在铜扩散阻挡层的顶表面上形成电介质层; （d）在所述电介质层中形成铜镶嵌或双镶嵌线，所述铜镶嵌件的顶表面或与所述电介质层的顶表面共面的双镶嵌线; （e）在所述导线的顶表面和所述电介质层的顶表面上形成第一覆盖层; （f）在步骤（e）执行与所述集成电路相关的一个或多个表征程序之后; 和（g）在步骤（e）之后，在第一覆盖层的顶表面上形成第二覆盖层。

9. 发明授权

US07176119B2 Method of fabricating copper damascene and dual damascene interconnect wiring 失效
标题翻译：铜镶嵌和双镶嵌互连布线的制作方法
公开(公告)号：US07176119B2
公开(公告)日：2007-02-13
申请号：US10711456
申请日：2004-09-20
申请人： Jeffrey P. Gambino , William Hill , Kenneth F. McAvey, Jr. , Thomas L. McDevitt , Anthony K. Stamper , Arthur C. Winslow , Robert Zwonik
发明人： Jeffrey P. Gambino , William Hill , Kenneth F. McAvey, Jr. , Thomas L. McDevitt , Anthony K. Stamper , Arthur C. Winslow , Robert Zwonik
IPC分类号： H01L21/4763
CPC分类号： H01L21/76832 , H01L21/76802 , H01L21/76807 , H01L21/76834
摘要： An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.
摘要翻译：一种集成电路和集成电路的制造方法，所述方法包括：（a）提供衬底; （b）在所述基板上形成铜扩散阻挡层; （c）在铜扩散阻挡层的顶表面上形成电介质层; （d）在所述电介质层中形成铜镶嵌或双镶嵌线，所述铜镶嵌件的顶表面或与所述电介质层的顶表面共面的双镶嵌线; （e）在所述导线的顶表面和所述电介质层的顶表面上形成第一覆盖层; （f）在步骤（e）执行与所述集成电路相关的一个或多个表征程序之后; 和（g）在步骤（e）之后，在第一覆盖层的顶表面上形成第二覆盖层。

10. 发明授权

US07087997B2 Copper to aluminum interlayer interconnect using stud and via liner 有权
公开(公告)号：US07087997B2
公开(公告)日：2006-08-08
申请号：US09805027
申请日：2001-03-12
申请人： Lloyd G. Burrell , Edward E. Cooney, III , Jeffrey P. Gambino , John E. Heidenreich, III , Hyun Koo Lee , Mark D. Levy , Baozhen Li , Stephen E. Luce , Thomas L. McDevitt , Anthony K. Stamper , Kwong Hon Wong , Sally J. Yankee
发明人： Lloyd G. Burrell , Edward E. Cooney, III , Jeffrey P. Gambino , John E. Heidenreich, III , Hyun Koo Lee , Mark D. Levy , Baozhen Li , Stephen E. Luce , Thomas L. McDevitt , Anthony K. Stamper , Kwong Hon Wong , Sally J. Yankee
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/76838 , H01L23/5226 , H01L23/53223 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.

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