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91. 发明申请

US20060286750A1 Method and system for forming straight word lines in a flash memory array 有权
公开(公告)号：US20060286750A1
公开(公告)日：2006-12-21
申请号：US11155707
申请日：2005-06-17
申请人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
发明人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7883 , H01L21/2652 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.

92. 发明申请

US20060284238A1 Non-volatile two-transistor programmable logic cell and array layout 有权
公开(公告)号：US20060284238A1
公开(公告)日：2006-12-21
申请号：US11155005
申请日：2005-06-15
申请人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
发明人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/0203 , H01L21/823493 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

93. 发明授权

US06754109B1 Method of programming memory cells 有权
标题翻译：编程存储单元的方法
公开(公告)号：US06754109B1
公开(公告)日：2004-06-22
申请号：US10282847
申请日：2002-10-29
申请人： Richard Fastow , Sameer Haddad , Zhigang Wang , Sheung-Hee Park
发明人： Richard Fastow , Sameer Haddad , Zhigang Wang , Sheung-Hee Park
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0483
摘要： In the present method of programming a selected flash EEPROM memory cell of a pair thereof in series, a positive voltage is applied to the drain of the selected cell to be programmed, a voltage lower than the voltage applied to the drain is applied to the source of the selected cell, a negative voltage is applied to the substrate, and a positive voltage is applied to the control gate sufficient to induce hot electron injection from the drain to the floating gate of the selected cell.
摘要翻译：在本文对串联选择的一对闪存EEPROM存储单元进行编程的方法中，将正电压施加到要被编程的选定单元的漏极，低于施加到漏极的电压的电压施加到源极，向基板施加负电压，并且将正电压施加到控制栅极，足以引起从漏极到所选电池的浮置栅极的热电子注入。

94. 发明授权

US09525756B2 Method and apparatus for invoking content of contact list 有权
公开(公告)号：US09525756B2
公开(公告)日：2016-12-20
申请号：US14360751
申请日：2012-01-13
申请人： Zhigang Wang
发明人： Zhigang Wang
IPC分类号： G06F15/16 , H04L29/08 , G06Q10/10 , H04M1/2745
CPC分类号： H04L67/32 , G06Q10/10 , H04L67/06 , H04M1/274558
摘要： The present disclosure discloses an apparatus for calling content of a contact list, including: a determining unit configured to send a shortcut adding unit a determining result that a shortcut to a contact list can be added in an Input Method Editor IME system; the shortcut adding unit configured to add the shortcut to the contact list in the IME system of a shortcut responding unit when receiving the determining result that the shortcut to the contact list can be added in the IME system sent by the determining unit; and the shortcut responding unit configured to save in the IME system the shortcut to the contact list sent by the shortcut adding unit, and call the contact list according to an operation of selecting the shortcut to the contact list from the IME system. The present disclosure also discloses a method for calling content of a contact list. With the present disclosure the content of a contact list can be called promptly without being limited by a category of content to be acquired or by a device.

95. 发明授权

US09226923B2 Spirocyclic molecules as protein kinase inhibitors 有权
标题翻译：螺环分子作为蛋白激酶抑制剂
公开(公告)号：US09226923B2
公开(公告)日：2016-01-05
申请号：US14234586
申请日：2012-07-26
申请人： Zhaoyin Wang , Lianhai Li , Zhigang Wang
发明人： Zhaoyin Wang , Lianhai Li , Zhigang Wang
IPC分类号： C07D401/14 , A61K31/4439 , A61K45/06
CPC分类号： A61K31/4439 , A61K45/06 , C07D401/14 , A61K2300/00
摘要： The present invention relates to spirocyclic compounds of formula I, namely spirocyclic (1H-pyrazol-4-yl)-3-(1-(2,6-dichloro-3-fluorophenyl)ethoxy)pyridin-2-amines having protein kinase inhibitory activity, and methods of synthesizing and using such compounds. Preferred compounds are c-Met and/or ALK inhibitors useful for the treatment of abnormal cell growth, such as cancers. R2 is selected from
摘要翻译：本发明涉及式I的螺环化合物，即具有蛋白激酶抑制性的螺环（1H-吡唑-4-基）-3-（1-（2,6-二氯-3-氟苯基）乙氧基）吡啶-2-胺活性，以及合成和使用这些化合物的方法。优选的化合物是用于治疗异常细胞生长的c-Met和/或ALK抑制剂，例如癌症。 R2选自

96. 发明授权

US08487251B2 Method for controlling charging of sample and scanning electron microscope 有权
标题翻译：用于控制样品充电的方法和扫描电子显微镜
公开(公告)号：US08487251B2
公开(公告)日：2013-07-16
申请号：US13059537
申请日：2009-08-08
申请人： Ritsuo Fukaya , Nobuhiro Okai , Koki Miyahara , Zhigang Wang
发明人： Ritsuo Fukaya , Nobuhiro Okai , Koki Miyahara , Zhigang Wang
IPC分类号： G01N23/00
CPC分类号： H01J37/026 , H01J37/09 , H01J37/15 , H01J37/28 , H01J2237/0041 , H01J2237/0045 , H01J2237/0458
摘要： An object of the present invention is to provide a scanning electron microscope aiming at making it possible to control the quantity of electrons generated by collision of electrons emitted from a sample with other members, and a sample charging control method using the control of electron quantity. To achieve the object, a scanning electron microscope including a plurality of apertures through which an electron beam can pass and a mechanism for switching the apertures for the electron beam, and a method for controlling sample charging by switching the apertures are proposed. The plurality of apertures are at least two apertures. Portions respectively having different secondary electron emission efficiencies are provided on peripheral portions of the at least two apertures on a side opposed to the sample. The quantity of electrons generated by collision of electrons emitted from the sample can be controlled by switching the apertures.
摘要翻译：本发明的目的是提供一种扫描电子显微镜，其目的在于可以控制从样品与其他部件发射的电子的碰撞产生的电子的量，以及使用电子量的控制的样品充电控制方法。为了实现该目的，提出了一种扫描电子显微镜，其包括电子束可以通过的多个孔，以及用于切换电子束的孔的机构，以及通过切换孔来控制样品充电的方法。多个孔是至少两个孔。分别具有不同二次电子发射效率的部分设置在与样品相对的一侧上的至少两个孔的周边部分上。可以通过切换孔来控制从样品发射的电子的碰撞产生的电子的量。

97. 发明申请

US20120318977A1 Scanning Electron Microscope Optical Condition Setting Method and Scanning Electron Microscope 有权
标题翻译：扫描电子显微镜光学条件设置方法和扫描电子显微镜
公开(公告)号：US20120318977A1
公开(公告)日：2012-12-20
申请号：US13578179
申请日：2011-02-09
申请人： Zhigang Wang , Nobuhiro Okai , Ritsuo Fukaya
发明人： Zhigang Wang , Nobuhiro Okai , Ritsuo Fukaya
IPC分类号： H01J37/26
CPC分类号： H01J37/28 , H01J37/026 , H01J37/244 , H01J2237/24592 , H01J2237/2817
摘要： It is an object of the present invention to provide an optical-condition setting method for a charged-particle beam device, and the charged-particle beam device which make it possible to set the following optical condition: Namely, an optical condition which allows the suppression of a lowering in the measurement and inspection accuracy caused by the influence of electrification, even if there exist a large number of measurement and inspection points.In order to accomplish the above-described object, the following scanning electron microscope or optical-condition setting method is proposed: Namely, a scanning electron microscope or an optical-condition setting method for measuring a pattern on a sample based on the detection of electrons, the electrons being emitted from the sample by scanning the sample surface with an electron beam, wherein a change in measurement values relative to the number of measurements is determined from the measurement values at a plurality of measurement points on the sample, and the sample-surface electric field is controlled so that the inclination of the change becomes equal to zero, or becomes close to zero.
摘要翻译：本发明的目的是提供一种带电粒子束装置的光学条件设定方法以及使得能够设定以下光学条件的带电粒子束装置：即，允许即使存在大量的测量点和检查点，也抑制了电气化影响引起的测量和检查精度的降低。为了实现上述目的，提出了以下扫描电子显微镜或光学条件设定方法：即，基于电子检测来测量样品上的图案的扫描电子显微镜或光学条件设定方法通过用电子束扫描样品表面从样品发射电子，其中相对于测量次数的测量值的变化根据样品上的多个测量点的测量值确定，控制表面电场使得变化的倾斜度等于零，或变得接近零。

98. 发明授权

US07898018B2 Non-volatile two-transistor programmable logic cell and array layout 有权
公开(公告)号：US07898018B2
公开(公告)日：2011-03-01
申请号：US12359481
申请日：2009-01-26
申请人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
发明人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/0203 , H01L21/823493 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

99. 发明授权

US07839681B2 Push-pull FPGA cell 有权
标题翻译：推挽FPGA单元
公开(公告)号：US07839681B2
公开(公告)日：2010-11-23
申请号：US12334059
申请日：2008-12-12
申请人： Zhigang Wang , Fethi Dhaoui , Michael Sadd , John McCollum , Frank Hawley
发明人： Zhigang Wang , Fethi Dhaoui , Michael Sadd , John McCollum , Frank Hawley
IPC分类号： G11C11/34
CPC分类号： G11C16/0441
摘要： A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.
摘要翻译：闪存单元包括具有源极，漏极，浮置栅极和控制栅极的p沟道闪存晶体管，具有源极的n沟道闪存晶体管，耦合到p沟道闪存晶体管的漏极的漏极，浮动栅极和控制栅极，具有耦合到p沟道闪存晶体管和n沟道闪存晶体管的漏极的栅极的开关晶体管，源极和漏极以及n沟道辅助晶体管，其具有漏极，其耦合到p沟道闪存晶体管和n沟道闪存晶体管的漏极，耦合到固定电位的源极和栅极。

100. 发明授权

US07721172B2 Method and apparatus for broadcasting test patterns in a scan-based integrated circuit 有权
标题翻译：用于在基于扫描的集成电路中广播测试模式的方法和装置
公开(公告)号：US07721172B2
公开(公告)日：2010-05-18
申请号：US12216640
申请日：2008-07-09
申请人： Laung-Terng (L.-T.) Wang , Boryau (Jack) Sheu , Zhigang Jiang , Zhigang Wang , Shianling Wu
发明人： Laung-Terng (L.-T.) Wang , Boryau (Jack) Sheu , Zhigang Jiang , Zhigang Wang , Shianling Wu
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G01R31/318547 , G01R31/318533 , G01R31/318591 , G01R31/31926
摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.The scan architecture used can also be random access scan based, where the integrated circuit comprises an array of random access scan (RAS) cells that are randomly and uniquely addressable. In random access scan, test patterns can be applied by selectively updating RAS cells and test responses can be observed through a direct read-out process. Eliminating the shifting process inherent in serial scan, random access scan produces much lower test power dissipation than serial scan.
摘要翻译：用于在基于扫描的集成电路中的ATE（自动测试设备）中降低测试数据量和测试应用时间的广播，系统和方法。基于扫描的集成电路包含多个扫描链，每个扫描链包括串联耦合的多个扫描单元。广播公司是组合逻辑网络，耦合到可选的虚拟扫描控制器和可选的扫描连接器。虚拟扫描控制器控制广播机构的操作。系统发送存储在ATE中的虚拟扫描模式，并通过广播机构生成广播扫描模式，以测试基于扫描的集成电路中的制造故障。 ATE可以支持的扫描链数显着增加。进一步提出了方法来重新排列所选择的扫描链中的扫描单元，以产生广播扫描图案和虚拟扫描图案，并且在基于扫描的集成电路中合成广播器和压缩器。所使用的扫描结构也可以是基于随机存取扫描的集成电路，其中集成电路包括随机访问扫描（RAS）阵列，其随机且唯一可寻址。在随机存取扫描中，可以通过选择性地更新RAS细胞来应用测试模式，并且可以通过直接读出过程来观察测试响应。消除串行扫描固有的移位过程，随机访问扫描产生比串行扫描低得多的测试功耗。

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