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1. 发明授权

US07839681B2 Push-pull FPGA cell 有权
标题翻译：推挽FPGA单元
公开(公告)号：US07839681B2
公开(公告)日：2010-11-23
申请号：US12334059
申请日：2008-12-12
申请人： Zhigang Wang , Fethi Dhaoui , Michael Sadd , John McCollum , Frank Hawley
发明人： Zhigang Wang , Fethi Dhaoui , Michael Sadd , John McCollum , Frank Hawley
IPC分类号： G11C11/34
CPC分类号： G11C16/0441
摘要： A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.
摘要翻译：闪存单元包括具有源极，漏极，浮置栅极和控制栅极的p沟道闪存晶体管，具有源极的n沟道闪存晶体管，耦合到p沟道闪存晶体管的漏极的漏极，浮动栅极和控制栅极，具有耦合到p沟道闪存晶体管和n沟道闪存晶体管的漏极的栅极的开关晶体管，源极和漏极以及n沟道辅助晶体管，其具有漏极，其耦合到p沟道闪存晶体管和n沟道闪存晶体管的漏极，耦合到固定电位的源极和栅极。

2. 发明申请

US20110024821A1 PUSH-PULL FPGA CELL 审中-公开
标题翻译：推拉FPGA单元
公开(公告)号：US20110024821A1
公开(公告)日：2011-02-03
申请号：US12903493
申请日：2010-10-13
申请人： Zhigang Wang , Fethi Dhaoui , Michael Sadd , John McCollum , Frank Hawley
发明人： Zhigang Wang , Fethi Dhaoui , Michael Sadd , John McCollum , Frank Hawley
IPC分类号： H01L29/68
CPC分类号： G11C16/0441
摘要： A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.
摘要翻译：闪存单元包括具有源极，漏极，浮置栅极和控制栅极的p沟道闪存晶体管，具有源极的n沟道闪存晶体管，耦合到p沟道闪存晶体管的漏极的漏极，浮动栅极和控制栅极，具有耦合到p沟道闪存晶体管和n沟道闪存晶体管的漏极的栅极的开关晶体管，源极和漏极以及n沟道辅助晶体管，其具有漏极，其耦合到p沟道闪存晶体管和n沟道闪存晶体管的漏极，耦合到固定电位的源极和栅极。

3. 发明申请

US20100149873A1 PUSH-PULL FPGA CELL 有权
标题翻译：推拉FPGA单元
公开(公告)号：US20100149873A1
公开(公告)日：2010-06-17
申请号：US12334059
申请日：2008-12-12
申请人： Zhigang Wang , Fethi Dhaoui , Michael Sadd , John McCollum , Frank Hawley
发明人： Zhigang Wang , Fethi Dhaoui , Michael Sadd , John McCollum , Frank Hawley
IPC分类号： G11C16/04 , G11C5/06
CPC分类号： G11C16/0441
摘要： A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.
摘要翻译：闪存单元包括具有源极，漏极，浮置栅极和控制栅极的p沟道闪存晶体管，具有源极的n沟道闪存晶体管，耦合到p沟道闪存晶体管的漏极的漏极，浮动栅极和控制栅极，具有耦合到p沟道闪存晶体管和n沟道闪存晶体管的漏极的栅极的开关晶体管，源极和漏极以及n沟道辅助晶体管，其具有漏极，其耦合到p沟道闪存晶体管和n沟道闪存晶体管的漏极，耦合到固定电位的源极和栅极。

4. 发明申请

US20100044768A1 REDUCED-EDGE RADIATION-TOLERANT NON-VOLATILE TRANSISTOR MEMORY CELLS 有权
标题翻译：降低辐射耐受非挥发性晶体管存储器细胞
公开(公告)号：US20100044768A1
公开(公告)日：2010-02-25
申请号：US12196978
申请日：2008-08-22
申请人： Michael Sadd , Fethi Dhaoui , John McCollum , Richard Chan
发明人： Michael Sadd , Fethi Dhaoui , John McCollum , Richard Chan
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11565 , H01L27/11568 , H01L29/66825 , H01L29/66833
摘要： An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. An edgeless two-transistor programmable memory includes memory cells that have two active devices. Two polysilicon gate layers overlay two active regions and are shared between the two active devices. One of the devices is used to program and erase the cell while the other used as a programmable switch in a programmable logic device. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region.
摘要翻译：无边形单晶体管闪存阵列包括具有覆盖有源区域的两个多晶硅栅极层的晶体管。底部多晶硅栅极层被电隔离。存储器被配置为使得电流在底部多晶硅层下方从漏极流到源极，使得其不接近场氧化物区域。无刃双晶体管可编程存储器包括具有两个有源器件的存储器单元。两个多晶硅栅极层覆盖两个有源区，并在两个有源器件之间共享。其中一个器件用于编程和擦除单元，而另一个用作可编程逻辑器件中的可编程开关。底部多晶硅栅极层被电隔离。存储器被配置为使得电流在底部多晶硅层下方从漏极流到源极，使得其不接近场氧化物区域。

5. 发明授权

US07906805B2 Reduced-edge radiation-tolerant non-volatile transistor memory cells 有权
标题翻译：降低辐射耐受性的非易失性晶体管存储单元
公开(公告)号：US07906805B2
公开(公告)日：2011-03-15
申请号：US12196978
申请日：2008-08-22
申请人： Michael Sadd , Fethi Dhaoui , John McCollum , Richard Chan
发明人： Michael Sadd , Fethi Dhaoui , John McCollum , Richard Chan
IPC分类号： H01L29/788
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11565 , H01L27/11568 , H01L29/66825 , H01L29/66833
摘要： An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. An edgeless two-transistor programmable memory includes memory cells that have two active devices. Two polysilicon gate layers overlay two active regions and are shared between the two active devices. One of the devices is used to program and erase the cell while the other used as a programmable switch in a programmable logic device. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region.
摘要翻译：无边形单晶体管闪存阵列包括具有覆盖有源区域的两个多晶硅栅极层的晶体管。底部多晶硅栅极层被电隔离。存储器被配置为使得电流在底部多晶硅层下方从漏极流到源极，使得其不接近场氧化物区域。无刃双晶体管可编程存储器包括具有两个有源器件的存储器单元。两个多晶硅栅极层覆盖两个有源区，并在两个有源器件之间共享。其中一个器件用于编程和擦除单元，而另一个用作可编程逻辑器件中的可编程开关。底部多晶硅栅极层被电隔离。存储器被配置为使得电流在底部多晶硅层下方从漏极流到源极，使得其不接近场氧化物区域。

6. 发明授权

US08633548B2 Non-volatile programmable memory cell and array for programmable logic array 有权
标题翻译：用于可编程逻辑阵列的非易失性可编程存储单元和阵列
公开(公告)号：US08633548B2
公开(公告)日：2014-01-21
申请号：US12894441
申请日：2010-09-30
申请人： Fethi Dhaoui , John McCollum , Frank Hawley , Leslie Richard Wilkinson
发明人： Fethi Dhaoui , John McCollum , Frank Hawley , Leslie Richard Wilkinson
IPC分类号： H01L29/76
CPC分类号： H01L27/11517 , G11C16/0433 , H01L27/105 , H01L27/11807
摘要： A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
摘要翻译：适用于可编程逻辑阵列的非易失性可编程存储单元包括与第二导电类型的易失性MOS晶体管串联的第一导电类型的非易失性MOS晶体管。非挥发性MOS晶体管可以是诸如闪存晶体管的浮动栅极晶体管，或者可以是诸如浮动电荷捕获SONOS，MONOS晶体管或纳米晶体管的另一种类型的非易失性晶体管。可以通过将其栅极或输入耦合到非易失性MOS晶体管和易失性MOS晶体管之间的公共连接来驱动易失性MOS晶体管，反相器或缓冲器。

7. 发明申请

US20080169498A1 NON-VOLATILE PROGRAMMABLE MEMORY CELL AND ARRAY FOR PROGRAMMABLE LOGIC ARRAY 失效
标题翻译：非易失可编程存储器单元和阵列可编程逻辑阵列
公开(公告)号：US20080169498A1
公开(公告)日：2008-07-17
申请号：US12054633
申请日：2008-03-25
申请人： Fethi Dhaoui , John McCollum , Frank Hawley , Leslie Wilkinson
发明人： Fethi Dhaoui , John McCollum , Frank Hawley , Leslie Wilkinson
IPC分类号： H01L29/788
CPC分类号： H01L27/11517 , G11C16/0433 , H01L27/105 , H01L27/11807
摘要： A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
摘要翻译：适用于可编程逻辑阵列的非易失性可编程存储单元包括与第二导电类型的易失性MOS晶体管串联的第一导电类型的非易失性MOS晶体管。非挥发性MOS晶体管可以是诸如闪存晶体管的浮动栅极晶体管，或者可以是诸如浮动电荷捕获SONOS，MONOS晶体管或纳米晶体管的另一种类型的非易失性晶体管。可以通过将其栅极或输入耦合到非易失性MOS晶体管和易失性MOS晶体管之间的公共连接来驱动易失性MOS晶体管，反相器或缓冲器。

8. 发明授权

US07538379B1 Non-volatile two-transistor programmable logic cell and array layout 有权
公开(公告)号：US07538379B1
公开(公告)日：2009-05-26
申请号：US11303865
申请日：2005-12-16
申请人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , William C. Plants , Zhigang Wang
发明人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , William C. Plants , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/11524 , H01L27/0203 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11526 , H01L27/11529 , H01L29/7881
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

9. 发明授权

US07692972B1 Split gate memory cell for programmable circuit device 有权
标题翻译：用于可编程电路器件的分离存储单元
公开(公告)号：US07692972B1
公开(公告)日：2010-04-06
申请号：US12177680
申请日：2008-07-22
申请人： Michael Sadd , Fethi Dhaoui , George Wang , John McCollum
发明人： Michael Sadd , Fethi Dhaoui , George Wang , John McCollum
IPC分类号： G11C16/04
CPC分类号： G11C16/0425 , G11C16/0441 , G11C16/0458 , G11C16/0466 , G11C16/0475
摘要： A split-gate memory cell, includes an n-channel split-gate non-volatile memory transistor having a source, a drain, a select gate over a thin oxide, and a control gate over a non-volatile gate material and separated from the select gate by a gap. A p-channel pull-up transistor has a drain coupled to the drain of the split-gate non-volatile memory transistor, a source coupled to a bit line, and a gate. A switch transistor has first and second source/drain diffusions, and a gate coupled to the drains of the split-gate non-volatile memory transistor and the p-channel pull-up transistor. An inverter has an input coupled to the second source/drain diffusion of the switch transistor, and an output. A p-channel level-restoring transistor has a source coupled to a supply potential, a drain coupled to the first source/drain diffusion of the switch transistor and a gate coupled to the output of the inverter.
摘要翻译：分离栅极存储单元包括具有源极，漏极，薄氧化物上的选择栅极和非易失性栅极材料上的控制栅极的n沟道分离栅极非易失性存储器晶体管，并且与选择一个缺口的门。 p沟道上拉晶体管具有耦合到分离栅极非易失性存储晶体管的漏极的漏极，耦合到位线的源极和栅极。开关晶体管具有第一和第二源极/漏极扩散，以及耦合到分离栅极非易失性存储晶体管和p沟道上拉晶体管的漏极的栅极。反相器具有耦合到开关晶体管的第二源/漏扩散的输入端和输出端。 p沟道电平恢复晶体管具有耦合到电源电位的源极，耦合到开关晶体管的第一源极/漏极扩散器的漏极和耦合到反相器的输出端的栅极。

10. 发明申请

US20110018070A1 NON-VOLATILE PROGRAMMABLE MEMORY CELL AND ARRAY FOR PROGRAMMABLE LOGIC ARRAY 有权
标题翻译：非易失可编程存储器单元和阵列可编程逻辑阵列
公开(公告)号：US20110018070A1
公开(公告)日：2011-01-27
申请号：US12894441
申请日：2010-09-30
申请人： Fethi Dhaoui , John McCollum , Frank Hawley , Leslie Richard Wilkinson
发明人： Fethi Dhaoui , John McCollum , Frank Hawley , Leslie Richard Wilkinson
IPC分类号： H01L27/092
CPC分类号： H01L27/11517 , G11C16/0433 , H01L27/105 , H01L27/11807
摘要： A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
摘要翻译：适用于可编程逻辑阵列的非易失性可编程存储单元包括与第二导电类型的易失性MOS晶体管串联的第一导电类型的非易失性MOS晶体管。非挥发性MOS晶体管可以是诸如闪存晶体管的浮动栅极晶体管，或者可以是诸如浮动电荷捕获SONOS，MONOS晶体管或纳米晶体管的另一种类型的非易失性晶体管。可以通过将其栅极或输入耦合到非易失性MOS晶体管和易失性MOS晶体管之间的公共连接来驱动易失性MOS晶体管，反相器或缓冲器。

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