专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20050190608A1 Method of forming a CMOS structure having gate insulation films of different thicknesses 有权
标题翻译：形成具有不同厚度的栅极绝缘膜的CMOS结构的方法
公开(公告)号：US20050190608A1
公开(公告)日：2005-09-01
申请号：US11118951
申请日：2005-05-02
申请人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
发明人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
IPC分类号： H01L21/8234 , H01L27/088 , G11C11/34
CPC分类号： H01L21/823857 , B82Y99/00 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/82385 , H01L27/088 , H01L27/0883 , H01L29/42364 , Y10S438/981 , Y10S977/936
摘要： The present invention is drawn to a semiconductor integrated circuit device employing employs on the same silicon substrate a plurality of kinds of MOS transistors with different in magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units. The control circuit is responsive to receipt of a control signal supplied thereto for controlling the flow of a current either between the source and gate or between the drain and gate of the tunnel current increased MOS transistor for use with the main circuit in such a way that the current flow is selectively permitted during certain time period and that it is inhibited during another period.
摘要翻译：本发明涉及一种半导体集成电路器件，其采用在同一硅衬底上采用在源极和栅极之间或其漏极和栅极之间流动的隧道电流大小不同的多种MOS晶体管。这些MOS晶体管包括隧道电流增加的MOS晶体管，其中至少一个用于构成器件的主电路。多种MOS晶体管还包括隧道电流减少或耗尽的MOS晶体管，其中至少一个用于控制电路。该控制电路插入在主电路和两个电源单元中的至少一个之间。控制电路响应于接收到提供给其的控制信号，以控制在主电路使用的隧道电流增加的MOS晶体管的源极和栅极之间或漏极和栅极之间的电流的流动，在一段时间内选择性地允许电流，并且在另一时段期间被禁止。

92. 发明授权

US06785165B2 Semiconductor device 有权
公开(公告)号：US06785165B2
公开(公告)日：2004-08-31
申请号：US10309238
申请日：2002-12-04
申请人： Takayuki Kawahara , Nozomu Matsuzaki , Terumi Sawase , Masaharu Kubo
发明人： Takayuki Kawahara , Nozomu Matsuzaki , Terumi Sawase , Masaharu Kubo
IPC分类号： G11C1604
CPC分类号： H01L29/792 , G11C16/0425 , G11C16/0466 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42324 , H01L29/42332 , H01L29/7885
摘要： A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.

93. 发明授权

US06500715B2 Method of forming a CMOS structure having gate insulation films of different thicknesses 有权
标题翻译：形成具有不同厚度的栅极绝缘膜的CMOS结构的方法
公开(公告)号：US06500715B2
公开(公告)日：2002-12-31
申请号：US09852793
申请日：2001-05-11
申请人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
发明人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
IPC分类号： H01L218234
CPC分类号： H01L21/823857 , B82Y99/00 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/82385 , H01L27/088 , H01L27/0883 , H01L29/42364 , Y10S438/981 , Y10S977/936
摘要： The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units. The control circuit is responsive to receipt of a control signal supplied thereto for controlling the flow of a current either between the source and gate or between the drain and gate of the tunnel-current increased MOS transistor for use with the main circuit in such a way that the current flow is selectively permitted during certain time period and that it is inhibited during another period.
摘要翻译：本发明涉及一种半导体集成电路器件，该半导体集成电路器件在相同的硅衬底上采用在源极和栅极之间或其漏极和栅极之间流动的隧道电流大小不同的多种MOS晶体管。这些MOS晶体管包括隧道电流增加的MOS晶体管，其中至少一个用于构成器件的主电路。多种MOS晶体管还包括隧道电流减小或耗尽的MOS晶体管，其中至少一个用于控制电路。该控制电路插入在主电路和两个电源单元中的至少一个之间。控制电路响应于接收到提供给其的控制信号，以控制在主电路使用的隧道电流增加的MOS晶体管的源极和栅极之间或漏极和栅极之间的电流的流动，以这种方式在一段时间内选择性地允许电流，并且在另一个时间段内禁止电流。

94. 发明授权

US5619151A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5619151A
公开(公告)日：1997-04-08
申请号：US473742
申请日：1995-06-07
申请人： Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yuji Yokoyama , Nozomu Matsuzaki , Tatsumi Yamauchi , Yutaka Kobayashi , Nobuyuki Gotou , Akira ide , Masahiro Yamamura , Hideaki Uchida
发明人： Takashi Akioka , Masahiro Iwamura , Atsushi Hiraishi , Yuji Yokoyama , Nozomu Matsuzaki , Tatsumi Yamauchi , Yutaka Kobayashi , Nobuyuki Gotou , Akira ide , Masahiro Yamamura , Hideaki Uchida
IPC分类号： G11C7/10 , G11C8/06 , G11C8/10 , G11C8/18 , H03K5/1534 , H03K19/0175 , H03K5/153 , G01R29/02 , H03K3/033
CPC分类号： G11C7/1057 , G11C7/1051 , G11C8/06 , G11C8/10 , G11C8/18 , H03K19/017518 , H03K5/1534
摘要： A semiconductor memory device which includes at least one of (1) an input buffer circuit which generates internal address signals in response to an incoming address; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.
摘要翻译：一种半导体存储器件，包括以下中的至少一个：（1）响应于输入地址产生内部地址信号的输入缓冲器电路; （2）由多个逻辑门形成的解码器电路，每个逻辑门由MOS和双极电路的组合组成; （3）包括多端子晶体管的读出放大器电路; （4）信号或地址转换检测器电路，其包括各自接收例如电压幅度的地址信号并且响应于地址信号的电平的变化而输出当前振幅信号的输入电路，以及连接的检测器电路具有共源共栅放大器，其布置成使得其在其输入处接收电流幅度信号，并且其中共源共栅放大器输入保持在基本上恒定的电压，其中检测电路检测到一个或多个当前幅度信号的转变并且响应于此产生电压幅度的ATD信号; 以及（5）输出缓冲器电路，其中根据响应于ATD信号的时钟发生器的信号来控制器件的解码器，读出放大器和输出缓冲器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式