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91. 发明授权

US07804700B2 Semiconductor memory device with reduced coupling noise 有权
标题翻译：具有降低耦合噪声的半导体存储器件
公开(公告)号：US07804700B2
公开(公告)日：2010-09-28
申请号：US12343086
申请日：2008-12-23
申请人： Yasutoshi Yamada , Tomonori Sekiguchi , Riichiro Takemura , Kazuhiko Kajigaya
发明人： Yasutoshi Yamada , Tomonori Sekiguchi , Riichiro Takemura , Kazuhiko Kajigaya
IPC分类号： G11C5/06 , G11C11/34 , G11C7/00
CPC分类号： G11C7/02 , G11C7/12 , G11C7/18 , G11C8/04 , G11C8/08 , G11C8/12 , G11C11/4094 , G11C11/4097
摘要： A semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at the intersections of the plurality of word lines and the plurality of bit lines and each of that includes a MIS transistor and a memory element, a decoder circuit for selecting a plurality of word lines, and a sense-amplifier circuit for determining information that is read from any of the plurality of memory cells to any of the plurality of bit lines, wherein a twist connector for switching the wiring order of the plurality of word lines is provided and level-stabilizing circuits, for supplying the potential level of a non-selected state to the plurality of word lines in the non-selected state are arranged in the area below the twist connector.
摘要翻译：半导体器件包括多个字线，多个位线，设置在多个字线和多个位线的交点处的多个存储单元，其中每一个包括MIS晶体管和存储元件，用于选择多个字线的解码器电路，以及用于确定从多个存储单元中的任何一个读取到多个位线中的任一个的信息的读出放大器电路，其中，用于切换多个字线的布线顺序的扭转连接器提供多个字线，并且用于将未选择状态的电位电平提供给未选择状态的多个字线的电平稳定电路被布置在扭转连接器下方的区域中。

92. 发明授权

US07772911B2 Timing control circuit and semiconductor storage device 有权
标题翻译：定时控制电路和半导体存储设备
公开(公告)号：US07772911B2
公开(公告)日：2010-08-10
申请号：US12208978
申请日：2008-09-11
申请人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
发明人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
IPC分类号： G06F1/04
CPC分类号： H03K5/135 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C11/4076 , G11C19/00
摘要： Disclosed is a timing control circuit that receives a first clock having a period T1, a group of second clocks of L different phases spaced apart from each other at substantially equal intervals and selection signals m, n supplied thereto and generates a fine timing signal delayed from the rising edge of the first clock signal by a delay td of approximately td=m·T1+n·(T2/L). The timing control circuit includes a coarse delay circuit and a fine delay circuit. The coarse delay circuit includes a counter for counting a rising edge of the first clock signal after an activate signal is activated and generates a coarse timing signal whose amount of delay from the first clock signal is approximately m·T1. The fine delay circuit comprises L-number of multiphase clock control delay circuits disposed in parallel, delays by n·T2/L the timing of sampling of the coarse timing signal by respective clocks of the group of L-phase second clocks, and takes the OR among the resulting delayed pulses to thereby produce the fine timing signal.
摘要翻译：公开了一种定时控制电路，其接收具有周期T1的第一时钟，以相等间隔彼此间隔开的L个不同相位的一组第二时钟，以及提供给其的选择信号m，n，并产生从第一时钟信号的上升沿大约为td = m·T1 + n·（T2 / L）的延迟td。定时控制电路包括粗延迟电路和精细延迟电路。粗略延迟电路包括用于在激活信号被激活之后对第一时钟信号的上升沿进行计数的计数器，并产生其第一时钟信号的延迟量大约为m·T1的粗略定时信号。精细延迟电路包括L个并联设置的多相时钟控制延迟电路，通过n·T2 / L延迟由L组第二时钟组的相应时钟对粗略定时信号进行采样的定时，或者产生延迟脉冲，从而产生精细定时信号。

93. 发明授权

US07706208B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07706208B2
公开(公告)日：2010-04-27
申请号：US12354549
申请日：2009-01-15
申请人： Riichiro Takemura , Tomonori Sekiguchi
发明人： Riichiro Takemura , Tomonori Sekiguchi
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C5/025 , G11C5/04 , G11C7/18 , G11C11/4097 , H01L25/0657 , H01L27/0207 , H01L27/10814 , H01L2224/4826 , H01L2924/13091 , H01L2924/00
摘要： If memory cell blocks are laid out in a conventional manner to create a memory chip with a capacity of an odd power of 2 by using memory cells whose aspect ratio is 1:2, the chip will take a 1:1 shape and become difficult to enclose in a package of a 1:2 shape. In addition, such conventional layout of memory cell blocks to form the 1:2 shape causes the area of a peripheral circuit region to be limited by the memory blocks, pads to be arranged collectively in the central section of the chip, and wiring to become dense during the enclosure of the chip in the package.In this invention, therefore, four memory blocks, BANK0, BANK1, BANK2, BANK3, BANK3, are constructed into an L shape and then these memory blocks are properly combined and arranged to construct a chip of nearly a 1:2 shape in terms of aspect ratio.
摘要翻译：如果通过使用纵横比为1:2的存储单元，以常规方式布置存储单元块以创建具有2的奇数功率的容量的存储芯片，则芯片将采取1：1的形状并变得难以以1：2的形状包装。此外，存储单元块的这种传统布局形成1：2形状会导致外围电路区域的区域受到存储块的限制，焊盘将被集中布置在芯片的中心部分中，并且布线成为密封在芯片封装中的封装。因此，在本发明中，将四个存储块BANK0，BANK1，BANK2，BANK3，BANK3构造成L形，然后将这些存储块适当地组合并布置成构成近似1：2形状的芯片长宽比。

94. 发明授权

US07613038B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07613038B2
公开(公告)日：2009-11-03
申请号：US12352668
申请日：2009-01-13
申请人： Riichiro Takemura , Takeshi Sakata , Norikatsu Takaura , Kazuhiko Kajigaya
发明人： Riichiro Takemura , Takeshi Sakata , Norikatsu Takaura , Kazuhiko Kajigaya
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.
摘要翻译：实现了高集成度和高速度的非易失性存储器，其可以在短的操作周期时间内稳定相变存储器的操作。在写入驱动器中提供锁存器。通过写使能信号，每列循环执行相变元件的高电阻状态的改变，并且在预充电命令被输入之后执行到其低电阻状态的改变，并且同时具有去激活的预充电信号。由此，对相变电阻变为低电阻状态的存储单元的写入时间，以及从相变电阻改变为高电阻状态到读操作的写操作的周期可以延长上述存储单元，而不延长列周期时间，从而实现稳定的写操作。

95. 发明申请

US20090175064A1 SEMICONDUCTOR MEMORY DEVICE WITH REDUCED COUPLING NOISE 有权
标题翻译：具有减少耦合噪声的半导体存储器件
公开(公告)号：US20090175064A1
公开(公告)日：2009-07-09
申请号：US12343086
申请日：2008-12-23
申请人： Yasutoshi Yamada , Tomonori Sekiguchi , Riichiro Takemura , Kazuhiko Kajigaya
发明人： Yasutoshi Yamada , Tomonori Sekiguchi , Riichiro Takemura , Kazuhiko Kajigaya
IPC分类号： G11C5/06 , G11C11/34 , G11C7/00
CPC分类号： G11C7/02 , G11C7/12 , G11C7/18 , G11C8/04 , G11C8/08 , G11C8/12 , G11C11/4094 , G11C11/4097
摘要： A semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at the intersections of the plurality of word lines and the plurality of bit lines and each of that includes a MIS transistor and a memory element, a decoder circuit for selecting a plurality of word lines, and a sense-amplifier circuit for determining information that is read from any of the plurality of memory cells to any of the plurality of bit lines, wherein a twist connector for switching the wiring order of the plurality of word lines is provided and level-stabilizing circuits, for supplying the potential level of a non-selected state to the plurality of word lines in the non-selected state are arranged in the area below the twist connector.
摘要翻译：半导体器件包括多个字线，多个位线，设置在多个字线和多个位线的交点处的多个存储单元，其中每一个包括一个MIS晶体管和一个存储元件，用于选择多个字线的解码器电路，以及用于确定从多个存储单元中的任何一个读取到多个位线中的任一个的信息的读出放大器电路，其中，用于切换多个字线的布线顺序的扭转连接器提供多个字线，并且用于将未选择状态的电位电平提供给未选择状态的多个字线的电平稳定电路被布置在扭转连接器下方的区域中。

96. 发明申请

US20090146716A1 Timing control circuit, timing generation system, timing control method and semiconductor memory device 有权
标题翻译：定时控制电路，定时生成系统，定时控制方法和半导体存储器件
公开(公告)号：US20090146716A1
公开(公告)日：2009-06-11
申请号：US12314207
申请日：2008-12-05
申请人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
发明人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
IPC分类号： H03H11/26
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C19/00 , H03K5/131 , H03K5/14 , H03K2005/00058 , H03K2005/00241
摘要： A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.
摘要翻译：定时控制电路DLY1接收具有周期T1和激活信号ACT的时钟信号CKa，并从m表示非负整数的时钟信号输出延迟m * T1 + tda的精确定时信号FT，并且tda表示模拟延迟元件定时控制电路DLY1包括粗延迟电路CD和精细延迟电路FD。粗延迟电路CD包括用于在接收到激活信号ACT之后对时钟信号CKa的上升沿进行计数的计数器，并输出从时钟信号CKa的上升沿测量的具有延迟m * T1的粗定时信号CT。精细延迟电路FD包括多个模拟延迟元件，并输出从粗定时信号CT测得的具有延迟tda的精细延迟定时信号FT。定时信号延迟的变化减小。

97. 发明申请

US20090059702A1 Sense amplifier for semiconductor memory device 有权
标题翻译：用于半导体存储器件的检测放大器
公开(公告)号：US20090059702A1
公开(公告)日：2009-03-05
申请号：US12285527
申请日：2008-10-08
申请人： Tomonori Sekiguchi , Shinichi Miyatake , Takeshi Sakata , Riichiro Takemura , Hiromasa Noda , Kazuhiko Kajigaya
发明人： Tomonori Sekiguchi , Shinichi Miyatake , Takeshi Sakata , Riichiro Takemura , Hiromasa Noda , Kazuhiko Kajigaya
IPC分类号： G11C7/06
CPC分类号： G11C7/062 , G11C5/063 , G11C7/065 , G11C7/08 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/18 , G11C8/08 , G11C11/4087 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C29/1201 , G11C2207/002 , G11C2207/005 , H01L27/0207 , H01L27/10814 , H01L27/10882 , H01L27/10897
摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.
摘要翻译：本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。

98. 发明授权

US07492644B2 Semiconductor integrated circuit device 有权
公开(公告)号：US07492644B2
公开(公告)日：2009-02-17
申请号：US11832727
申请日：2007-08-02
申请人： Riichiro Takemura , Takeshi Sakata , Norikatsu Takaura , Kazuhiko Kajigaya
发明人： Riichiro Takemura , Takeshi Sakata , Norikatsu Takaura , Kazuhiko Kajigaya
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.

99. 发明授权

US07489552B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07489552B2
公开(公告)日：2009-02-10
申请号：US11501118
申请日：2006-08-09
申请人： Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
发明人： Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
IPC分类号： G11C11/34
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0071 , G11C2013/0078 , G11C2013/009 , G11C2213/76 , G11C2213/79
摘要： In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate voltage of a memory cell selection transistor QM is controlled to afford a low resistance state, the maximum amount of current applied to the phase change portion is limited by the application of a medium-state voltage to the control gate, thereby avoiding overheating of the phase change portion.
摘要翻译：在非易失性相变存储器中，利用相变部分的电阻变化来记录信息。当相变部分产生焦耳热并保持在特定温度时，其进入低电阻状态。当控制存储单元选择晶体管QM的栅极电压以提供低电阻状态时，通过向控制栅极施加中等电压来限制施加到相变部分的最大电流量，从而避免过热的相变部。

100. 发明申请

US20090014770A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090014770A1
公开(公告)日：2009-01-15
申请号：US12169789
申请日：2008-07-09
申请人： Motoyasu Terao , Hideyuki Matsuoka , Naohiko Irie , Yoshitaka Sasago , Riichiro Takemura , Norikatsu Takaura
发明人： Motoyasu Terao , Hideyuki Matsuoka , Naohiko Irie , Yoshitaka Sasago , Riichiro Takemura , Norikatsu Takaura
IPC分类号： H01L29/00
CPC分类号： H01L45/145 , G11C11/5614 , G11C13/0011 , G11C2213/11 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146
摘要： A technique that can realize high integration even for multilayered three-dimensional structures at low costs by improving the performance of the semiconductor device having recording or switching functions by employing a device structure that enables high precision controlling of the movement of ions in the solid electrolyte. The semiconductor element of the device is formed as follows; two or more layers are deposited with different components respectively between a pair of electrodes disposed separately in the vertical (z-axis) direction, then a pulse voltage is applied between those electrodes to form a conductive path. The resistance value of the path changes according to an information signal. Furthermore, a region is formed at a middle part of the conductive path. The region is used to accumulate a component that improves the conductivity of the path, thereby enabling the resistance value (rate) to response currently to the information signal. More preferably, an electrode should also be formed at least in either the x-axis or y-axis direction to apply a control voltage to the electrode.
摘要翻译：通过采用能够高精度地控制固体电解质中的离子的运动的装置结构，通过提高具有记录或切换功能的半导体器件的性能，可以以低成本实现多层次三维结构的高集成度的技术。器件的半导体元件如下形成; 分别在垂直（z轴）方向上分开设置的一对电极之间分别沉积两层或更多层，然后在这些电极之间施加脉冲电压以形成导电路径。路径的电阻值根据信息信号而变化。此外，在导电路径的中间部分形成区域。该区域用于累积改善路径的导电性的分量，从而使电阻值（速率）能够当前响应于信息信号。更优选地，电极也应至少形成在x轴方向或y轴方向上，以向电极施加控制电压。

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