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91. 发明申请

US20080065854A1 Method and apparatus for accessing physical memory belonging to virtual machines from a user level monitor 审中-公开
标题翻译：用于从用户级监视器访问属于虚拟机的物理内存的方法和装置
公开(公告)号：US20080065854A1
公开(公告)日：2008-03-13
申请号：US11517668
申请日：2006-09-07
申请人： Sebastina Schoenberg , Udo Steinberg , Alain Kaegi , Tariq Masood , Philip Lantz , Andrew V. Anderson
发明人： Sebastina Schoenberg , Udo Steinberg , Alain Kaegi , Tariq Masood , Philip Lantz , Andrew V. Anderson
IPC分类号： G06F12/00 , G06F13/00 , G06F9/34
CPC分类号： G06F13/28 , G06F9/45537 , G06F12/1036 , G06F12/109
摘要： A processing system may include a service operating system (OS) and a guest virtual machine (VM). The service OS may be a host OS or an OS in a service VM, for instance. The guest VM may have a physical address space. In one embodiment, a pseudo-device driver in the service OS causes an address within the physical address space of the guest VM to be mapped to an address within a virtual address space of a user level monitor (ULM) running on top of the service OS. When an operation that involves the physical address space of the guest VM (e.g., a direct memory access (DMA) operation requested by the guest VM, an interrupt triggered by the guest VM, etc.) is detected, the ULM may use its virtual address space to access the physical address space of the guest VM. Other embodiments are described and claimed.
摘要翻译：处理系统可以包括服务操作系统（OS）和来宾虚拟机（VM）。例如，服务OS可以是服务VM中的主机OS或OS。访客虚拟机可能具有物理地址空间。在一个实施例中，服务操作系统中的伪设备驱动程序使访客虚拟机的物理地址空间内的地址映射到在服务之上运行的用户级监视器（ULM）的虚拟地址空间内的地址操作系统。当检测到涉及访客VM的物理地址空间的操作（例如，来宾VM请求的直接存储器访问（DMA）操作，由客户VM触发的中断等））时，ULM可以使用其虚拟访问虚拟机的物理地址空间的地址空间。描述和要求保护其他实施例。

92. 发明授权

US06529968B1 DMA controller and coherency-tracking unit for efficient data transfers between coherent and non-coherent memory spaces 失效
公开(公告)号：US06529968B1
公开(公告)日：2003-03-04
申请号：US09469171
申请日：1999-12-21
申请人： Andrew V. Anderson
发明人： Andrew V. Anderson
IPC分类号： G06F1314
CPC分类号： G06F13/1668
摘要： In a computer system, an agent, a DMA controller and a memory controller are provided, each in communication with a bus. The DMA controller and the memory controller also can communicate with each other via a second communication path. The computer system may include a memory provided in communication with the memory controller having a coherent memory space and a non-coherent memory space. The DMA controller transfers a portion of data from the coherent memory space with a portion of data from the non-coherent memory space with a single transaction on the external bus.

93. 发明授权

US06345009B1 Apparatus and method for refreshing subsets of memory devices in a memory system 有权
标题翻译：用于刷新存储器系统中存储器件子集的装置和方法
公开(公告)号：US06345009B1
公开(公告)日：2002-02-05
申请号：US09658465
申请日：2000-09-08
申请人： Ely K. Tsern , Richard M. Barth , Paul G. Davis , Craig E. Hampel , Thomas J. Holman , Andrew V. Anderson
发明人： Ely K. Tsern , Richard M. Barth , Paul G. Davis , Craig E. Hampel , Thomas J. Holman , Andrew V. Anderson
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A memory system includes a set of memory devices. An interconnect structure links the set of memory devices to one another. A memory controller is connected to the interconnect structure. The memory controller is configured to apply a control signal to the interconnect structure such that a specified subset of the set of memory devices performs a refresh operation.
摘要翻译：存储器系统包括一组存储器件。互连结构将存储器件集合彼此连接。存储器控制器连接到互连结构。存储器控制器被配置为将控制信号施加到互连结构，使得该组存储器件的指定子集执行刷新操作。

94. 发明授权

US09563557B2 Instruction and logic for flush-on-fail operation 有权
标题翻译：刷新失败操作的指令和逻辑
公开(公告)号：US09563557B2
公开(公告)日：2017-02-07
申请号：US14580632
申请日：2014-12-23
申请人： Sanjay Kumar , Rajesh M. Sankaran , Subramanya R. Dulloor , Andrew V. Anderson
发明人： Sanjay Kumar , Rajesh M. Sankaran , Subramanya R. Dulloor , Andrew V. Anderson
IPC分类号： G06F12/00 , G06F13/00 , G06F12/08
CPC分类号： G06F12/0804 , G06F9/467 , G06F11/07 , G06F11/073 , G06F11/0778 , G06F11/0793 , G06F11/14 , G06F11/1482 , G06F12/0868 , G06F2201/805 , G06F2201/82 , G06F2212/1032 , G06F2212/608
摘要： A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.
摘要翻译：处理器包括存储器管理单元和包括解码器的前端。解码器包括用于在与FoC指令相关联的存储的承诺时接收刷新提交（FoC）指令以将脏数据从易失性高速缓冲器刷新到持久存储器的逻辑。存储器管理单元包括基于刷新失败（FoF）模式的逻辑，跳过刷新提交指令的执行，并且在随后的FoF操作时从易失性高速缓存清除脏数据。

95. 发明申请

US20110016290A1 Method and Apparatus for Supporting Address Translation in a Multiprocessor Virtual Machine Environment 审中-公开
标题翻译：在多处理器虚拟机环境中支持地址转换的方法和装置
公开(公告)号：US20110016290A1
公开(公告)日：2011-01-20
申请号：US12460105
申请日：2009-07-14
申请人： Arie Chobotaro , Rinat Rappoport , Andrew V. Anderson , Baruch Chaikin
发明人： Arie Chobotaro , Rinat Rappoport , Andrew V. Anderson , Baruch Chaikin
IPC分类号： G06F12/10
CPC分类号： G06F9/45558 , G06F2009/45566 , G06F2009/45583
摘要： In one embodiment, a method includes receiving control of a first processor transitioned from a virtual machine due to a privileged event pertaining to a translation-lookaside buffer, and determining which entries in a guest translation data structure were modified by the virtual machine. The determination is made based on metadata extracted from a shadow translation data structure maintained by a virtual machine monitor and attributes associated with entries in the shadow translation data structure. The metadata includes an active entry list identifying mappings that map pages used by a guest operating system in forming the guest translation data structure. The method further includes synchronizing entries in the shadow translation data structure that correspond to the modified entries in the guest translation data structure with the modified entries in the guest translation data structure, and determining which entries to keep in the active entry list, based at least in part on attributes associated with corresponding entries in the shadow translation data structure identifying which of the plurality of processors owns each entry in the active entry list.
摘要翻译：在一个实施例中，一种方法包括接收由于与翻译后备缓冲器有关的特权事件而从虚拟机转换的第一处理器的控制，以及确定客体翻译数据结构中的哪些条目被虚拟机修改。基于从由虚拟机监视器维护的阴影翻译数据结构提取的元数据和与阴影翻译数据结构中的条目相关联的属性进行确定。元数据包括标识映射的活动条目列表，其映射由客户操作系统在形成客体翻译数据结构中使用的页面。所述方法还包括将所述客体翻译数据结构中与修改的条目相对应的影子翻译数据结构中的条目与访客翻译数据结构中的修改的条目同步，以及至少基于部分地关于与阴影翻译数据结构中的对应条目相关联的属性，其识别多个处理器中的哪个处理器拥有活动条目列表中的每个条目。

96. 发明申请

US20090172346A1 TRANSITIONING BETWEEN SOFTWARE COMPONENT PARTITIONS USING A PAGE TABLE POINTER TARGET LIST 审中-公开
标题翻译：软件组件分段之间的转换使用一个页表指针目标列表
公开(公告)号：US20090172346A1
公开(公告)日：2009-07-02
申请号：US11967500
申请日：2007-12-31
申请人： Ravi Sahita , Uday R. Savagaonkar , David M. Durham , Andrew V. Anderson , Ulhas Warrier
发明人： Ravi Sahita , Uday R. Savagaonkar , David M. Durham , Andrew V. Anderson , Ulhas Warrier
IPC分类号： G06F9/26
CPC分类号： G06F12/145 , G06F9/5077
摘要： Embodiments of apparatuses, articles, methods, and systems for intra-partitioning components within an execution environment, and transitioning between partitions using a page table pointer target list are generally described herein. Other embodiments may be described and claimed.
摘要翻译：这里一般地描述使用页表指针目标列表在执行环境内进行分区内组件的设备，物品，方法和系统的实施例以及在分区之间的转换。可以描述和要求保护其他实施例。

97. 发明授权

US07395405B2 Method and apparatus for supporting address translation in a virtual machine environment 有权
标题翻译：用于在虚拟机环境中支持地址转换的方法和装置
公开(公告)号：US07395405B2
公开(公告)日：2008-07-01
申请号：US11045524
申请日：2005-01-28
申请人： Andrew V. Anderson , Alain Kägi
发明人： Andrew V. Anderson , Alain Kägi
IPC分类号： G06F12/00 , G06F21/00 , G06F9/26 , G06F9/34 , G06F9/455
CPC分类号： G06F12/1036 , G06F9/45558 , G06F2009/45583
摘要： In one embodiment, a method includes receiving control transitioned from a virtual machine (VM) due to a privileged event pertaining to a translation-lookaside buffer (TLB), and determining which entries in a guest translation data structure were modified by the VM. The determination is made based on metadata extracted from a shadow translation data structure maintained by a virtual machine monitor (VMM) and attributes associated with entries in the shadow translation data structure. The method further includes synchronizing entries in the shadow translation data structure that correspond to the modified entries in the guest translation data structure with the modified entries in the guest translation data structure.
摘要翻译：在一个实施例中，一种方法包括接收由于与翻译后备缓冲器（TLB）有关的特权事件而从虚拟机（VM）转换的控制，以及确定客户转换数据结构中哪些条目被VM修改。基于从由虚拟机监视器（VMM）维护的阴影翻译数据结构提取的元数据和与阴影翻译数据结构中的条目相关联的属性进行确定。该方法还包括将客体翻译数据结构中与经修改的条目相对应的影子翻译数据结构中的条目与访客翻译数据结构中的修改的条目同步。

98. 发明授权

US06651115B2 DMA controller and coherency-tracking unit for efficient data transfers between coherent and non-coherent memory spaces 有权
标题翻译： DMA控制器和一致性跟踪单元，用于在相干和非相干存储空间之间进行有效的数据传输
公开(公告)号：US06651115B2
公开(公告)日：2003-11-18
申请号：US10336720
申请日：2003-01-06
申请人： Andrew V. Anderson
发明人： Andrew V. Anderson
IPC分类号： G06F1314
CPC分类号： G06F13/1668
摘要： In a computer system, an agent, a DMA controller and a memory controller are provided, each in communication with a bus. The DMA controller and the memory controller also can communicate with each other via a second communication path. The computer system may include a memory provided in communication with the memory controller having a coherent memory space and a non-coherent memory space. The DMA controller transfers a portion of data from the coherent memory space with a portion of data from the non-coherent memory space with a single transaction on the external bus.
摘要翻译：在计算机系统中，提供代理，DMA控制器和存储器控制器，每个与总线通信。 DMA控制器和存储器控制器也可以经由第二通信路径相互通信。计算机系统可以包括与具有相干存储器空间和非相干存储器空间的存储器控制器通信提供的存储器。 DMA控制器使用来自非相干存储器空间的一部分数据从相干存储器空间与外部总线上的单个事务传输一部分数据。

99. 发明授权

US06594730B1 Prefetch system for memory controller 有权
标题翻译：内存控制器预取系统
公开(公告)号：US06594730B1
公开(公告)日：2003-07-15
申请号：US09365851
申请日：1999-08-03
申请人： Herbert H J Hum , Andrew V. Anderson
发明人： Herbert H J Hum , Andrew V. Anderson
IPC分类号： G06F1300
CPC分类号： G06F13/1673
摘要： An embodiment of the present invention provides a memory controller that includes a plurality of transaction queues and an arbiter, a prefetch cache in communication with the arbiter, and a prefetch queue in communication with the prefetch cache. The prefetch queue also may be provided in communication with each of the transaction queues for the purpose of determining whether the transaction queues are operating in a congested state.
摘要翻译：本发明的实施例提供一种存储器控制器，其包括多个事务队列和仲裁器，与仲裁器通信的预取高速缓存器，以及与预取缓存通信的预取队列。为了确定事务队列是否处于拥塞状态，预取队列还可以被提供与每个事务队列通信。

100. 发明授权

US06378018B1 Memory device and system including a low power interface 有权
标题翻译：存储器件和系统包括低功率接口
公开(公告)号：US06378018B1
公开(公告)日：2002-04-23
申请号：US09169506
申请日：1998-10-09
申请人： Ely K. Tsern , Thomas J. Holman , Richard M. Barth , Andrew V. Anderson , Paul G. Davis , Craig E. Hampel , Donald C. Stark , Abhijit M. Abhyankar
发明人： Ely K. Tsern , Thomas J. Holman , Richard M. Barth , Andrew V. Anderson , Paul G. Davis , Craig E. Hampel , Donald C. Stark , Abhijit M. Abhyankar
IPC分类号： G06F1300
CPC分类号： G06F13/4243 , G06F13/1694 , Y02D10/14 , Y02D10/151
摘要： A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power interface for coupling to the low speed channel. The memory device is operative in a low power mode and a high power mode. A memory controller is coupled to the high speed channel and the low speed channel of the interconnect structure. The memory controller is configured to transmit control information over the low speed channel to set the power mode of the memory device. The memory device is operative in a low power mode during which high power receiver circuits are turned off. The memory device is also operative in a nap mode during which an internal clock compensation circuit is left on to preserve phase information. The memory system may include multiple memory devices coupled to a daisy chained lead of the interconnect structure. The memory controller may be configured to apply control information to the interconnect structure as an encoded device identification word. The memory devices may each include a decoder for interpreting the encoded device identification word. The memory controller may be configured to apply a memory device selection signal to the interconnect structure to selectively enable the memory devices.
摘要翻译：存储器系统包括具有高速通道和低速通道的互连结构。具有接口电路的存储器件耦合到互连结构。接口电路包括用于耦合到高速通道的高功率接口和用于耦合到低速通道的低功率接口。存储器件在低功率模式和高功率模式下工作。存储器控制器耦合到互连结构的高速通道和低速通道。存储器控制器被配置为通过低速信道发送控制信息以设置存储器件的功率模式。存储器件在低功率模式下工作，在此期间高功率接收器电路被关闭。存储器装置还可以在休眠模式下工作，在此模式期间内部时钟补偿电路被保留以保持相位信息。存储器系统可以包括耦合到互连结构的菊花链引导件的多个存储器件。存储器控制器可以被配置为将控制信息作为编码设备标识字应用于互连结构。存储器件可以各自包括用于解释编码器件识别字的解码器。存储器控制器可以被配置为将存储器件选择信号施加到互连结构以选择性地启用存储器件。

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