专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US08218708B2 Phase splitter using digital delay locked loops 失效
标题翻译：分相器使用数字延迟锁定环路
公开(公告)号：US08218708B2
公开(公告)日：2012-07-10
申请号：US12987431
申请日：2011-01-10
申请人： Feng Lin , R. Jacob Baker
发明人： Feng Lin , R. Jacob Baker
IPC分类号： H03D3/24
CPC分类号： H03L7/0805 , H03K5/15013 , H03L7/0814 , H03L7/0818 , H03L7/087 , H03L7/089
摘要： A phase splitter uses digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.
摘要翻译：分相器使用数字延迟锁定环（DLL）来接收互补输入时钟信号以产生具有不同相移的多个输出信号。当DLL被锁定时，分相器的延迟分辨率等于DLL的两个延迟级。

92. 发明授权

US08149646B2 Digital filters for semiconductor devices 有权
标题翻译：用于半导体器件的数字滤波器
公开(公告)号：US08149646B2
公开(公告)日：2012-04-03
申请号：US12829251
申请日：2010-07-01
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： G11C8/00
CPC分类号： G11C16/26 , G11C7/02 , G11C7/067 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/04 , G11C16/0483 , G11C27/005 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2211/5634 , G11C2211/5644
摘要： A memory device that, in certain embodiments, includes a memory element and a digital filter. The digital filter may include a counter and a divider, where the divider is configured to divide a count from the counter by a divisor.
摘要翻译：在某些实施例中，包括存储元件和数字滤波器的存储器件。数字滤波器可以包括计数器和分频器，其中分频器被配置为将来自计数器的计数除以除数。

93. 发明授权

US08068046B2 Methods of quantizing signals using variable reference signals 有权
标题翻译：使用可变参考信号量化信号的方法
公开(公告)号：US08068046B2
公开(公告)日：2011-11-29
申请号：US12776242
申请日：2010-05-07
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： H03M1/56
CPC分类号： G11C16/26 , G11C7/06 , H03M3/39 , H03M3/43 , H03M3/456
摘要： Methods for reading a data location coupled to an electrical conductor. A counter receives a signal from an analog-to-digital converter coupled to the electrical conductor. The counter produces two or more counts, and in some embodiments, the counts are based in part on a variable reference voltage. An interfuser may be coupled to an output of the counter. The interfuser receives the two or more counts from the counter and reads data conveyed by the data location based on the two or more counts.
摘要翻译：读取耦合到电导体的数据位置的方法。计数器从耦合到电导体的模数转换器接收信号。计数器产生两个或多个计数，并且在一些实施例中，计数部分地基于可变参考电压。接口用户可以耦合到计数器的输出。接口用户从计数器接收两个或多个计数，并且基于两个或更多个计数读取由数据位置传送的数据。

94. 发明授权

US08042012B2 Systems and devices including memory with built-in self test and methods of making and using the same 有权
标题翻译：系统和设备，包括具有内置自检功能的内存，以及使用它们的方法
公开(公告)号：US08042012B2
公开(公告)日：2011-10-18
申请号：US12903936
申请日：2010-10-13
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/04 , G11C29/026 , G11C29/028 , G11C29/38 , G11C29/40
摘要： Disclosed are methods, systems and devices, such as a device including a data location, a quantizing circuit coupled to the data location, and a test module coupled to the quantizing circuit. The quantizing circuit may include an analog-to-digital converter, a switch coupled to the memory element and a feedback signal path coupled to the output of the analog-to-digital converter and to the switch.
摘要翻译：公开了方法，系统和设备，例如包括数据位置的设备，耦合到数据位置的量化电路以及耦合到量化电路的测试模块。量化电路可以包括模拟 - 数字转换器，耦合到存储器元件的开关和耦合到模数转换器的输出和开关的反馈信号路径。

95. 发明授权

US07877623B2 Method and apparatus for providing symmetrical output data for a double data rate DRAM 有权
标题翻译：为双数据速率DRAM提供对称输出数据的方法和装置
公开(公告)号：US07877623B2
公开(公告)日：2011-01-25
申请号：US12222216
申请日：2008-08-05
申请人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
发明人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
IPC分类号： G06F13/42
CPC分类号： G11C7/1066 , G06F1/10 , G06F1/12 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , H03L7/0814
摘要： An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.
摘要翻译：公开了一种用于补偿来自逻辑电路（例如存储器件）的用于同步输出信号（例如数据信号或定时信号）的本地处理的系统时钟的偏斜和不对称性的装置和方法。公开了第一相位检测器，延迟锁定环（DLL）延迟元件和伴随电路的阵列，以与系统时钟XCLK信号的上升沿相位锁定输出信号的上升沿。此外，公开了比较器电路，寄存器延迟，DLL延迟元件阵列和伴随电路，以从DQ信号的下降沿增加或减去延迟，以产生DQ信号的对称输出。

96. 发明申请

US20110013465A1 INTEGRATORS FOR DELTA-SIGMA MODULATORS 有权
标题翻译： DELTA-SIGMA调制器的集成器
公开(公告)号：US20110013465A1
公开(公告)日：2011-01-20
申请号：US12886377
申请日：2010-09-20
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： G11C7/06
CPC分类号： G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C2211/5634 , G11C2211/5644 , H03K3/0231 , H03M1/60
摘要： Methods, systems and devices are disclosed. Among the disclosed devices is an electronic device that, in certain embodiments, includes a plurality of memory elements or imaging elements connected to a bit-line and a delta-sigma modulator connected to the bit-line. The delta-sigma modulator may include an integrator having a differential amplifier.
摘要翻译：公开了方法，系统和装置。所公开的设备中的电子设备是在某些实施例中包括连接到与位线连接的位线和Δ-Σ调制器的多个存储器元件或成像元件的电子设备。 Δ-Σ调制器可以包括具有差分放大器的积分器。

97. 发明授权

US07873131B2 Phase splitter using digital delay locked loops 有权
标题翻译：分相器使用数字延迟锁定环路
公开(公告)号：US07873131B2
公开(公告)日：2011-01-18
申请号：US11216778
申请日：2005-08-31
申请人： Feng Lin , R. Jacob Baker
发明人： Feng Lin , R. Jacob Baker
IPC分类号： H03D3/24
CPC分类号： H03L7/0805 , H03K5/15013 , H03L7/0814 , H03L7/0818 , H03L7/087 , H03L7/089
摘要： A phase splitter using digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.
摘要翻译：一种使用数字延迟锁定环（DLL）来接收互补输入时钟信号以产生具有不同相移的多个输出信号的分相器。当DLL被锁定时，分相器的延迟分辨率等于DLL的两个延迟级。

98. 发明申请

US20100073993A1 MULTI-RESISTIVE INTEGRATED CIRCUIT MEMORY 有权
标题翻译：多电阻集成电路存储器
公开(公告)号：US20100073993A1
公开(公告)日：2010-03-25
申请号：US12626110
申请日：2009-11-25
申请人： R. Jacob Baker , Kurt D. Beigel
发明人： R. Jacob Baker , Kurt D. Beigel
IPC分类号： G11C11/00 , G11C11/02
CPC分类号： H01L28/82 , G11C5/04 , G11C11/15 , H01L23/5223 , H01L27/0214 , H01L27/0805 , H01L2924/0002 , Y10S257/905 , Y10S257/906 , Y10S257/908 , H01L2924/00
摘要： A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.
摘要翻译：用于集成电路的电容器包括一层导电材料。所述导电材料层包括至少第一部分和第二部分，其中所述第一部分和所述第二部分相对于彼此以预定图案布置，以提供每半导体管芯面积的最大量的电容。

99. 发明授权

US07667632B2 Quantizing circuits for semiconductor devices 有权
标题翻译：半导体器件的量化电路
公开(公告)号：US07667632B2
公开(公告)日：2010-02-23
申请号：US11818999
申请日：2007-06-15
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： H03M1/12
CPC分类号： H03M1/504 , G11C7/02 , G11C7/04 , G11C7/1006 , G11C7/16 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C2211/5634 , G11C2211/5644 , H03M3/39 , H03M3/43 , H03M3/456
摘要： An electronic device that includes an internal data storage location coupled to an electrical conductor and a quantizing circuit coupled to the internal data storage location via the electrical conductor. In some embodiments, the quantizing circuit includes an analog-to-digital converter having an input and an output, where the input is coupled to the electrical conductor and a digital filter coupled to the output of the analog-to-digital converter.
摘要翻译：一种电子设备，包括耦合到电导体的内部数据存储位置和经由电导体耦合到内部数据存储位置的量化电路。在一些实施例中，量化电路包括具有输入和输出的模数转换器，其中输入耦合到电导体，以及耦合到模数转换器的输出的数字滤波器。

100. 发明授权

US07577044B2 Resistive memory element sensing using averaging 有权
标题翻译：电阻式存储元件感应使用平均
公开(公告)号：US07577044B2
公开(公告)日：2009-08-18
申请号：US12049426
申请日：2008-03-17
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： G11C11/02 , G01R27/14
CPC分类号： G01R27/02 , G11C11/16 , G11C11/1659 , G11C11/1673 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element to maintain a constant voltage across the resistive element. The charge reservoir is connected to the voltage supply to provide a current through the resistive element. The current source is connected to the charge reservoir to repeatedly supply a pulse of current to recharge the reservoir upon depletion of electronic charge from the reservoir, and the pulse counter provides a count of the number of pulses supplied by the current source over a predetermined time. The count represents a logic state of the memory cell element.
摘要翻译：一种用于确定电阻性存储单元元件（例如MRAM电阻单元元件）的逻辑状态的系统。该系统包括受控电压源，电子充电储存器，电流源和脉冲计数器。受控电压源连接到电阻存储单元元件，以在电阻元件两端保持恒定的电压。电荷储存器连接到电压源以提供通过电阻元件的电流。电流源连接到电荷储存器，以在从储存器耗尽电荷时重复地提供电流脉冲以对储存器再充电，并且脉冲计数器在预定时间内提供由电流源提供的脉冲数的计数。计数表示存储单元元件的逻辑状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式