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91. 发明授权

US06740566B2 Ultra-thin resist shallow trench process using high selectivity nitride etch 有权
标题翻译：使用高选择性氮化物蚀刻的超薄抗蚀剂浅沟槽工艺
公开(公告)号：US06740566B2
公开(公告)日：2004-05-25
申请号：US09398641
申请日：1999-09-17
申请人： Christopher F. Lyons , Scott A. Bell , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Chih Yuh Yang
发明人： Christopher F. Lyons , Scott A. Bell , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Chih Yuh Yang
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： In one embodiment, the present invention relates to a method of forming a shallow trench, involving the steps of providing a semiconductor substrate comprising a barrier oxide layer over at the semiconductor substrate and a nitride layer over the barrier oxide layer; depositing an ultra-thin photoresist over the nitride layer, the ultra-thin photoresist having a thickness of about 2,000 Å or less; patterning the ultra-thin photoresist to expose a portion of the nitride layer and to define a pattern for the shallow trench; etching the exposed portion of the nitride layer with an etchant having a nitride:photoresist selectivity of at least about 10:1 to expose a portion of the barrier oxide layer; etching the exposed portion of the barrier oxide layer to expose a portion of the semiconductor substrate; and etching the exposed portion of the semiconductor substrate to provide the shallow trench. In another embodiment, the method further involves depositing an insulating filler material into the shallow trench to provide a shallow trench isolation region.
摘要翻译：在一个实施例中，本发明涉及一种形成浅沟槽的方法，包括以下步骤：在半导体衬底上提供包括阻挡氧化物层的半导体衬底，以及在阻挡氧化物层上方的氮化物层; 在所述氮化物层上沉积超薄光致抗蚀剂，所述超薄光致抗蚀剂具有约2,000或更小的厚度; 图案化超薄光致抗蚀剂以暴露氮化物层的一部分并且限定用于浅沟槽的图案; 用具有至少约10:1的氮化物：光致抗蚀剂选择性的蚀刻剂蚀刻氮化物层的暴露部分以暴露部分阻挡氧化物层; 蚀刻阻挡氧化物层的暴露部分以暴露半导体衬底的一部分; 并蚀刻半导体衬底的暴露部分以提供浅沟槽。在另一个实施例中，该方法还包括将绝缘填充材料沉积到浅沟槽中以提供浅沟槽隔离区域。

92. 发明授权

US06684172B1 Sensor to predict void free films using various grating structures and characterize fill performance 失效
标题翻译：传感器预测使用各种光栅结构的无空隙膜，并表征填充性能
公开(公告)号：US06684172B1
公开(公告)日：2004-01-27
申请号：US10034165
申请日：2001-12-27
申请人： Ramkumar Subramanian , Steven C. Avanzino , Christopher F. Lyons , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Cyrus E. Tabery
发明人： Ramkumar Subramanian , Steven C. Avanzino , Christopher F. Lyons , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Cyrus E. Tabery
IPC分类号： G01L2500
CPC分类号： C23C16/52 , C23C14/547 , C23C18/1675 , C25D21/12 , H01L21/76877
摘要： One aspect of the invention relates to a metal fill process and systems therefor involving providing a standard calibration wafer having a plurality of fill features of known dimensions in a metalization tool; depositing a metal material over the standard calibration wafer; monitoring the deposition of metal material using a sensor system, the sensor system operable to measure one or more fill process parameters and to generate fill process data; controlling the deposition of metal material to minimize void formation using a control system wherein the control system receives fill process data from the sensor system and analyzes the fill process data to generate a feed-forward control data operative to control the metalization tool; and depositing metal material over a production wafer in the metalization tool using the fill process data generated by the sensor system and the control system. The invention further relates to tool characterization processes and systems therefor.
摘要翻译：本发明的一个方面涉及一种金属填充方法及其系统，其涉及在金属化工具中提供具有已知尺寸的多个填充特征的标准校准晶片; 在标准校准晶片上沉积金属材料; 使用传感器系统监测金属材料的沉积，所述传感器系统可操作以测量一个或多个填充过程参数并产生填充过程数据; 控制金属材料的沉积以最小化使用控制系统的空隙形成，其中控制系统从传感器系统接收填充过程数据并分析填充过程数据以产生可操作以控制金属化工具的前馈控制数据; 以及使用由传感器系统和控制系统产生的填充过程数据在金属化工具中的生产晶片上沉积金属材料。本发明还涉及其工具表征过程及其系统。

93. 发明授权

US06623893B1 Pellicle for use in EUV lithography and a method of making such a pellicle 有权
标题翻译：用于EUV光刻的防护薄膜和制造这种防护薄膜的方法
公开(公告)号：US06623893B1
公开(公告)日：2003-09-23
申请号：US09770730
申请日：2001-01-26
申请人： Harry J. Levinson , Christopher F. Lyons
发明人： Harry J. Levinson , Christopher F. Lyons
IPC分类号： G03F900
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/24 , G03F1/62
摘要： A pellicle utilizes a film attached to a barrier layer above a substrate. The film is relatively transparent to radiation in the EUV range. The substrate and barrier layer are coupled to a periphery of the film and is exclusive of the center portion of the film. The pellicle can be manufactured by growing a relatively transparent film on a barrier layer that is grown on a substrate. The substrate and barrier layer are etched to expose a portion of the relatively transparent film.
摘要翻译：防护薄膜组件利用附着在衬底上方的阻挡层的膜。该电影对EUV范围内的辐射相对透明。衬底和阻挡层耦合到膜的周边，并且不包括膜的中心部分。可以通过在衬底上生长的阻挡层上生长相对透明的膜来制造防护薄膜组件。蚀刻衬底和阻挡层以暴露一部分相对透明的膜。

94. 发明授权

US06605413B1 Chemical treatment to strengthen photoresists to prevent pattern collapse 失效
标题翻译：化学处理加强光致抗蚀剂，防止图案崩溃
公开(公告)号：US06605413B1
公开(公告)日：2003-08-12
申请号：US10230171
申请日：2002-08-29
申请人： Christopher F. Lyons , Ramkumar Subramanian
发明人： Christopher F. Lyons , Ramkumar Subramanian
IPC分类号： G03F726
CPC分类号： G03F7/40 , G03F7/2024 , G03F7/405
摘要： There is provided a method for forming a photoresist layer for photolithographic applications which has increased structural strength. The photoresist layer is exposed through a mask and developed. The photoresist layer is then reacted with a stabilizer agent to change its material properties before the photoresist layer is dried. Also provided are a semiconductor fabrication method employing a stabilizer-treated photoresist and a composition for a photoresist that strengthens when exposed to a stabilizer agent.
摘要翻译：提供了一种用于形成光刻应用的光致抗蚀剂层的方法，其具有增加的结构强度。光致抗蚀剂层通过掩模曝光并显影。然后光致抗蚀剂层与稳定剂反应以在光致抗蚀剂层干燥之前改变其材料性质。还提供了使用稳定剂处理的光致抗蚀剂的半导体制造方法和当暴露于稳定剂时增强的光致抗蚀剂组合物。

95. 发明授权

US06566214B1 Method of making a semiconductor device by annealing a metal layer to form metal silicide and using the metal silicide as a hard mask to pattern a polysilicon layer 失效
标题翻译：通过退火金属层以形成金属硅化物并且使用金属硅化物作为硬掩模来制造半导体器件以图案化多晶硅层的方法
公开(公告)号：US06566214B1
公开(公告)日：2003-05-20
申请号：US10047036
申请日：2002-01-17
申请人： Christopher F. Lyons , Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat
发明人： Christopher F. Lyons , Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat
IPC分类号： H01L213213
CPC分类号： H01L21/28123
摘要： A method of making a semiconductor device is provided. A polysilicon layer is formed over a substrate and a metal layer is formed on the polysilicon layer. The metal layer and the polysilicon layer are annealed to form a metal silicide layer on the polysilicon layer. The metal silicide layer is patterned and the polysilicon layer is then patterned using the patterned metal silicide layer as a mask. The patterned metal silicide and polysilicon layers may be used as a gate electrode of a MOSFET.
摘要翻译：提供制造半导体器件的方法。在衬底上形成多晶硅层，并且在多晶硅层上形成金属层。退火金属层和多晶硅层，以在多晶硅层上形成金属硅化物层。图案化金属硅化物层，然后使用图案化的金属硅化物层作为掩模来对多晶硅层进行构图。图案化的金属硅化物和多晶硅层可以用作MOSFET的栅电极。

96. 发明授权

US06548423B1 Multilayer anti-reflective coating process for integrated circuit fabrication 有权
标题翻译：用于集成电路制造的多层抗反射涂层工艺
公开(公告)号：US06548423B1
公开(公告)日：2003-04-15
申请号：US10047971
申请日：2002-01-16
申请人： Marina V. Plat , Christopher F. Lyons , Scott A. Bell , Todd P. Lukanc
发明人： Marina V. Plat , Christopher F. Lyons , Scott A. Bell , Todd P. Lukanc
IPC分类号： H01L2131
CPC分类号： H01L21/0276 , G03F7/091 , H01L21/0332 , H01L21/28123 , H01L21/32139
摘要： A method utilizing a multilayer anti-reflective coating layer structure. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating.
摘要翻译：一种利用多层抗反射涂层结构的方法。多层抗反射涂层结构可以用作形成各种集成电路结构的硬掩模。可以使用多层抗反射涂层结构来形成由多晶硅和电介质层组成的栅叠层。在多层抗反射涂层上施加光致抗蚀剂。

97. 发明授权

US06544693B2 Pellicle for use in small wavelength lithography and a method for making such a pellicle 有权
公开(公告)号：US06544693B2
公开(公告)日：2003-04-08
申请号：US09770733
申请日：2001-01-26
申请人： Harry J. Levinson , Christopher F. Lyons
发明人： Harry J. Levinson , Christopher F. Lyons
IPC分类号： G03F900
CPC分类号： G03F1/62
摘要： A pellicle utilizes a thin film attached to a substrate. The film is relatively transparent to radiation. The substrate is coupled to a periphery of the film and is exclusive of the center portion of the film. The pellicle can be manufactured by growing a relatively transparent film on a substrate and etching the substrate to expose a portion of the relatively transparent film.

98. 发明授权

US06423650B1 Ultra-thin resist coating quality by increasing surface roughness of the substrate 有权
公开(公告)号：US06423650B1
公开(公告)日：2002-07-23
申请号：US09371715
申请日：1999-08-09
申请人： Marina V. Plat , Christopher F. Lyons , Michael K. Templeton , Bhanwar Singh
发明人： Marina V. Plat , Christopher F. Lyons , Michael K. Templeton , Bhanwar Singh
IPC分类号： H01L2131
摘要： In one embodiment, the present invention relates to a method of processing a semiconductor substrate, involving the steps of providing the semiconductor substrate having an upper surface; roughening the upper surface of the semiconductor substrate so that the upper surface of the semiconductor substrate has an Rtm of about 10 Å or more; and depositing an ultra-thin photoresist on the upper surface of the semiconductor substrate, the ultra-thin photoresist having a thickness of about 2,000 Å or less.

99. 发明授权

US06391525B1 Sidewall patterning for sub 100 nm gate conductors 失效
标题翻译：用于亚100 nm栅极导体的侧壁图案化
公开(公告)号：US06391525B1
公开(公告)日：2002-05-21
申请号：US09482256
申请日：2000-01-13
申请人： Christopher F. Lyons
发明人： Christopher F. Lyons
IPC分类号： G03F700
CPC分类号： G03F7/00 , G03F7/0035 , G03F7/0045 , H01L21/0337 , H01L21/0338 , H01L21/28132 , H01L21/3088 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L21/76838 , H01L21/76885
摘要： In one embodiment, the present invention relates to a method of forming a circuit structure containing at least one sub-lithographic gate conductor involving the steps of providing a substrate comprising active regions and a preliminary gate conductor film over portions of the substrate and portions of the active regions; forming a sidewall template mask having at least one sidewall over a portion of the preliminary gate conductor film that is positioned over portions of the active regions; forming a sidewall film over the sidewall template mask, the sidewall film having a vertical portion adjacent the sidewall of the sidewall template mask and a horizontal portion in areas not adjacent the sidewall of the sidewall template mask; removing the horizontal portion of the sidewall film exposing a portion of the sidewall template mask and removing the sidewall template mask; providing a second mask over the portions of the preliminary gate conductor film that are not positioned over portions of the active regions; removing exposed portions of the preliminary gate conductor film thereby forming the circuit structure containing the sub-lithographic gate conductor and gate conductors; providing a trim mask over the active regions, portions of the sub-lithographic gate conductor and the gate conductors; and removing exposed portions of the sidewall film and portions of the preliminary gate conductor film under the sidewall film.
摘要翻译：在一个实施例中，本发明涉及一种形成包含至少一个子光刻栅极导体的电路结构的方法，该方法包括以下步骤：在衬底的部分上提供包括有源区和初步栅导体膜的衬底，活跃地区; 形成侧壁模板掩模，所述侧壁模板掩模具有位于所述有源区的部分上方的所述预选导体膜的一部分上的至少一个侧壁; 在所述侧壁模板掩模上形成侧壁膜，所述侧壁膜具有邻近所述侧壁模板掩模的侧壁的垂直部分和不邻近所述侧壁模板掩模的侧壁的区域中的水平部分; 去除暴露所述侧壁模板掩模的一部分并去除所述侧壁模板掩模的所述侧壁膜的水平部分; 在预置栅极导体膜的未位于有源区的部分上的部分上提供第二掩模; 去除预置栅极导体膜的暴露部分，从而形成包含副光刻栅极导体和栅极导体的电路结构; 在有源区域上提供修整掩模，在次光栅栅极导体和栅极导体的部分上; 并且除去侧壁膜的暴露部分和预侧栅导体膜的侧壁膜下面的部分。

100. 发明授权

US06380588B1 Semiconductor device having uniform spacers 有权
标题翻译：具有均匀间隔物的半导体器件
公开(公告)号：US06380588B1
公开(公告)日：2002-04-30
申请号：US09567013
申请日：2000-05-09
申请人： William G. En , Minh Van Ngo , Chih-Yuk Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
发明人： William G. En , Minh Van Ngo , Chih-Yuk Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
IPC分类号： H01L2100
CPC分类号： H01L21/31116
摘要： A semiconductor device having both functional and non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.
摘要翻译：具有功能和非功能或虚拟线，区域和/或图案的半导体器件，以产生导致随后形成的间隔物在形状和尺寸上更可预测和均匀的拓扑。

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