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91. 发明授权

US08004088B2 Post passivation interconnection schemes on top of IC chip 有权
公开(公告)号：US08004088B2
公开(公告)日：2011-08-23
申请号：US11854552
申请日：2007-09-13
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

92. 发明授权

US07973629B2 Method for making high-performance RF integrated circuits 有权
标题翻译：制造高性能RF集成电路的方法
公开(公告)号：US07973629B2
公开(公告)日：2011-07-05
申请号：US11930664
申请日：2007-10-31
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01F5/00
CPC分类号： H01L23/544 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/5227 , H01L28/10 , H01L2221/68327 , H01L2221/6834 , H01L2221/6835 , H01L2924/0002 , H01L2924/12044 , H01L2924/1423 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/00
摘要： A new method and structure is provided for the creation of a semiconductor inductor. Under the first embodiment of the invention, a semiconductor substrate is provided with a scribe line in a passive surface region and active circuits surrounding the passive region. At least one bond pad is created on the passive surface of the substrate close to and on each side of the scribe line. A layer of insulation is deposited, a layer of dielectric is deposited over the layer of insulation, at least one bond pad is provided on the surface of the layer of dielectric on each side of the scribe line. At least one inductor is created on each side of the scribe line on the surface of the layer of dielectric. A layer of passivation is deposited over the layer of dielectric. The substrate is attached to a glass panel by interfacing the surface of the layer of passivation with the glass panel. The substrate is sawed from the backside of the substrate in alignment with the scribe line. The silicon that remains in place in the passive surface of the substrate underneath the scribe lines is removed by etching, the glass panel is separated along the scribe line. Under the second embodiment of the invention, the inductor is created on the surface of a thick layer of polymer that is deposited over the layer of passivation.
摘要翻译：提供了一种新的制造半导体电感器的方法和结构。在本发明的第一实施例中，半导体衬底在无源表面区域中设有划线，并且在被动区域周围设有有源电路。在基板的被动表面上至少形成一个接合垫，该接合垫靠近划线的每侧。沉积一层绝缘层，在该绝缘层上沉积一层电介质，至少一个接合焊盘设置在刻划线两边的电介质层的表面上。在电介质层的表面上的划线的每侧形成至少一个电感器。一层钝化层沉积在电介质层上。通过将钝化层的表面与玻璃面板接合来将衬底附接到玻璃面板。衬底从衬底的背面锯切，与划刻线对准。通过蚀刻去除在划线下面的衬底的被动表面中残留的位置的硅，沿着划线分离玻璃面板。在本发明的第二个实施例中，电感器被形成在沉积在钝化层上的聚合物厚层的表面上。

93. 发明授权

US07969006B2 Integrated circuit chips with fine-line metal and over-passivation metal 有权
公开(公告)号：US07969006B2
公开(公告)日：2011-06-28
申请号：US11864917
申请日：2007-09-29
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Chien-Kang Chou
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Chien-Kang Chou
IPC分类号： H01L23/48
CPC分类号： H01L23/552 , H01L21/76816 , H01L21/76873 , H01L23/5283 , H01L23/5286 , H01L23/53238 , H01L23/5329 , H01L24/05 , H01L24/11 , H01L24/45 , H01L24/48 , H01L24/73 , H01L27/0251 , H01L2224/02166 , H01L2224/0231 , H01L2224/0401 , H01L2224/04042 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05664 , H01L2224/1148 , H01L2224/13022 , H01L2224/13099 , H01L2224/16145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2224/48664 , H01L2224/48724 , H01L2224/48747 , H01L2224/48764 , H01L2224/48824 , H01L2224/48847 , H01L2224/48864 , H01L2224/73257 , H01L2224/73265 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10253 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/01039 , H01L2924/00 , H01L2224/05552
摘要： An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.

94. 发明授权

US07915734B2 Chip structure and process for forming the same 有权
公开(公告)号：US07915734B2
公开(公告)日：2011-03-29
申请号：US12032706
申请日：2008-02-18
申请人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
发明人： Jin-Yuan Lee , Mou-Shiung Lin , Ching-Cheng Huang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L24/02 , H01L24/10 , H01L24/11 , H01L24/13 , H01L27/0248 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/0401 , H01L2224/05073 , H01L2224/0558 , H01L2224/05644 , H01L2224/05655 , H01L2224/05657 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/12044 , H01L2924/19041 , H01L2924/30105 , H01L2924/00
摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

95. 发明申请

US20100200898A1 IMAGE AND LIGHT SENSOR CHIP PACKAGES 有权
标题翻译：图像和光传感器芯片包
公开(公告)号：US20100200898A1
公开(公告)日：2010-08-12
申请号：US12703139
申请日：2010-02-09
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L31/02
CPC分类号： H01L31/0203 , H01L24/45 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/8592 , H01L2924/01015 , H01L2924/01047 , H01L2924/12042 , H01L2924/13091 , H01L2924/1461 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/20751 , H01L2924/00012
摘要： An image or light sensor chip package includes an image or light sensor chip having a non-photosensitive area and a photosensitive area surrounded by the non-photosensitive area. In the photosensitive area, there are light sensors, a layer of optical or color filter array over the light sensors and microlenses over the layer of optical or color filter array. In the non-photosensitive area, there are an adhesive polymer layer and multiple metal structures having a portion in the adhesive polymer layer. A transparent substrate is formed on a top surface of the adhesive polymer layer and over the microlenses. The image or light sensor chip package also includes wirebonded wires or a flexible substrate bonded with the metal structures of the image or light sensor chip.
摘要翻译：图像或光传感器芯片封装包括具有非感光区域和由非感光区域包围的感光区域的图像或光传感器芯片。在感光区域中有光传感器，光学或彩色滤光片阵列在光传感器和光学或彩色滤光片阵列上的微透镜之上。在非感光区域中，粘合聚合物层和粘合聚合物层中具有一部分的多个金属结构体。在粘合聚合物层的顶表面上并在微透镜上形成透明基底。图像或光传感器芯片封装还包括引线键合线或与图像或光传感器芯片的金属结构接合的柔性基板。

96. 发明授权

US07479450B2 Post passivation interconnection schemes on top of the IC chips 有权
公开(公告)号：US07479450B2
公开(公告)日：2009-01-20
申请号：US11861299
申请日：2007-09-26
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L21/4763
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

97. 发明授权

US07470988B2 Chip structure and process for forming the same 有权
标题翻译：芯片结构及其形成方法
公开(公告)号：US07470988B2
公开(公告)日：2008-12-30
申请号：US10997145
申请日：2004-11-24
申请人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
发明人： Mou-Shiung Lin , Jin-Yuan Lee , Ching-Cheng Huang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L28/10 , H01L21/768 , H01L21/76807 , H01L21/76838 , H01L23/522 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/60 , H01L24/02 , H01L24/10 , H01L24/11 , H01L24/13 , H01L27/0251 , H01L27/0676 , H01L27/08 , H01L28/20 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/0401 , H01L2224/13 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/12044 , H01L2924/14 , H01L2924/15174 , H01L2924/19041 , H01L2924/30105 , Y10T29/49124 , Y10T29/49204 , H01L2924/00
摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.
摘要翻译：芯片结构包括基板，第一堆叠层，钝化层和第二堆积层。基板包括放置在基板的表面上的许多电气装置。第一组合层位于基底上。第一组合层设置有第一电介质体和第一互连方案，其中第一互连方案与第一介电体内部交错并电连接到电气装置。第一互连方案由第一金属层和插塞构成，其中相邻的第一金属层通过插塞电连接。钝化层设置在第一堆叠层上并且设有暴露第一互连方案的开口。第二堆叠层形成在钝化层上。第二组合层设置有第二电介质体和第二互连方案，其中第二互连方案在第二介电体内部交织并与第一互连方案电连接。第二互连方案由至少一个第二金属层和至少一个通孔金属填料构成，其中第二金属层电连接到通孔金属填料。第二金属层的迹线的厚度，宽度和横截面积分别大于第一金属层的厚度，宽度和横截面面积。

98. 发明授权

US07466007B2 Post passivation interconnection schemes on top of IC chip 有权
公开(公告)号：US07466007B2
公开(公告)日：2008-12-16
申请号：US11856078
申请日：2007-09-17
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L29/00
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

99. 发明授权

US07459791B2 Post passivation interconnection schemes on top of IC chip 有权
公开(公告)号：US07459791B2
公开(公告)日：2008-12-02
申请号：US11856077
申请日：2007-09-17
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

100. 发明授权

US07419900B2 Post passivation interconnection schemes on top of the IC chips 有权
公开(公告)号：US07419900B2
公开(公告)日：2008-09-02
申请号：US11858904
申请日：2007-09-21
申请人： Mou-Shiung Lin , Jin-Yuan Lee
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L21/4763
CPC分类号： H01L23/60 , H01L21/768 , H01L21/76801 , H01L21/76838 , H01L23/5222 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/5286 , H01L23/5329 , H01L23/53295 , H01L23/62 , H01L24/05 , H01L27/0248 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

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