专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US07158398B2 Semiconductor memory device having row decoder in which high-voltage-applied portion is located adjacent to low-voltage-applied portion 失效
标题翻译：具有行解码器的半导体存储器件，其中高压施加部分位于与低电压施加部分相邻的位置
公开(公告)号：US07158398B2
公开(公告)日：2007-01-02
申请号：US11052792
申请日：2005-02-09
申请人： Akira Shimizu , Riichiro Shirota , Fumitaka Arai
发明人： Akira Shimizu , Riichiro Shirota , Fumitaka Arai
IPC分类号： G11C5/06
CPC分类号： G11C16/08 , G11C16/0483 , H01L27/105 , H01L27/115
摘要： A semiconductor memory device includes a first, second, and third memory cell transistors in which information can be electrically rewritten, addresses of which are consecutive in a row direction. One end of a current passage in each of a first, second, and third memory cell transistors is connected to a control electrode of the first, second, and third memory cell transistors. A write voltage, a pass voltage lower than the write voltage, and a first voltage lower than the pass voltage are applied to the other ends of the first, second, and third transfer transistors. A first control section applies the first on-voltage to make the first transfer transistor conductive, to a gate of the first transfer transistor. A second control section applies a second on-voltage to make the second and third transfer transistors conductive, to gates of the second and third transfer transistors.
摘要翻译：半导体存储器件包括第一，第二和第三存储单元晶体管，其中信息可被电重写，其地址在行方向上是连续的。第一，第二和第三存储单元晶体管中的每一个中的电流通路的一端连接到第一，第二和第三存储单元晶体管的控制电极。写入电压，低于写入电压的通过电压以及低于通过电压的第一电压施加到第一，第二和第三转移晶体管的另一端。第一控制部分将第一传导晶体管导通的第一导通电压施加到第一传输晶体管的栅极。第二控制部分施加第二导通电压以使第二和第三转移晶体管导通到第二和第三转移晶体管的栅极。

92. 发明授权

US07151686B2 Semiconductor memory device and electric device with the same 有权
标题翻译：半导体存储器件和电器件相同
公开(公告)号：US07151686B2
公开(公告)日：2006-12-19
申请号：US10944910
申请日：2004-09-21
申请人： Kikuko Sugimae , Takuya Futatsuyama , Riichiro Shirota , Masayuki Ichige
发明人： Kikuko Sugimae , Takuya Futatsuyama , Riichiro Shirota , Masayuki Ichige
IPC分类号： G11C17/00
CPC分类号： G11C8/12 , G11C8/10 , G11C16/08
摘要： A semiconductor memory device having: a cell array including bit lines, word lines and memory cells disposed at crossings thereof, plural memory cells being connected in series to constitute a NAND cell unit, plural blocks being arranged, each being constituted by plural NAND cell units arranged in the word line direction; and a row decoder configured to select a block, wherein the row decoder includes: transferring transistor arrays disposed in association with the blocks, in each of which transistors are arranged for transferring word line drive voltages; first decode portions disposed in association with the transferring transistor arrays, which are applied with boosted voltages to selectively drive the transferring transistor arrays; and second decode portions configured to select one of the blocks, each of which is disposed to be shared by adjacent two first decode portions.
摘要翻译：一种半导体存储器件，具有：包括位线，字线和位于其交叉处的存储单元的单元阵列，多个存储单元串联连接以构成NAND单元单元，多个块被布置，每个由多个NAND单元单元排列在字线方向; 以及配置为选择块的行解码器，其中所述行解码器包括：传送与所述块相关联地布置的晶体管阵列，其中每个晶体管布置用于传送字线驱动电压; 与传输晶体管阵列相关联地设置的第一解码部分，其被施加升压电压以选择性地驱动传输晶体管阵列; 以及第二解码部分，被配置为选择所述块之一，每个块被布置为由相邻的两个第一解码部分共享。

93. 发明申请

US20060262600A1 Non-Volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20060262600A1
公开(公告)日：2006-11-23
申请号：US11492994
申请日：2006-07-26
申请人： Riichiro Shirota , Kikuko Sugimae
发明人： Riichiro Shirota , Kikuko Sugimae
IPC分类号： G11C16/04
CPC分类号： H01L27/11526 , G11C16/0433 , H01L27/105 , H01L27/11521 , H01L27/11529 , H01L27/11558
摘要： A memory cell has a selection transistor constituted of an MOS transistor having a gate electrode and a cell transistor constituted of an MOS transistor having the same polarity as the selection transistor, in such a configuration that these two transistors are connected in series. A bit line is connected to a drain region of the selection transistor and a word line is connected to the gate electrode thereof. A gate electrode of the cell transistor is not electrically connected anywhere so as to be in a floating potential state, while a drain region thereof is connected to a source region of the selection transistor. A source line is connected to a source region of the cell transistor.
摘要翻译：存储单元具有由具有栅电极的MOS晶体管和由与选择晶体管具有相同极性的MOS晶体管构成的单元晶体管构成的选择晶体管，其结构是这两个晶体管串联连接。位线连接到选择晶体管的漏极区域，并且字线连接到其栅电极。单元晶体管的栅极电极不会在任何地方电连接，以便处于浮置电位状态，而其漏极区域连接到选择晶体管的源极区域。源极线连接到单元晶体管的源极区域。

94. 发明授权

US07095651B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07095651B2
公开(公告)日：2006-08-22
申请号：US11211633
申请日：2005-08-26
申请人： Riichiro Shirota , Kikuko Sugimae
发明人： Riichiro Shirota , Kikuko Sugimae
IPC分类号： G11C16/04 , G11C5/06
CPC分类号： H01L27/11526 , G11C16/0433 , H01L27/105 , H01L27/11521 , H01L27/11529 , H01L27/11558
摘要： A memory cell has a selection transistor constituted of an MOS transistor having a gate electrode and a cell transistor constituted of an MOS transistor having the same polarity as the selection transistor, in such a configuration that these two transistors are connected in series. A bit line is connected to a drain region of the selection transistor and a word line is connected to the gate electrode thereof. A gate electrode of the cell transistor is not electrically connected anywhere so as to be in a floating potential state, while a drain region thereof is connected to a source region of the selection transistor. A source line is connected to a source region of the cell transistor.
摘要翻译：存储单元具有由具有栅电极的MOS晶体管和由与选择晶体管具有相同极性的MOS晶体管构成的单元晶体管构成的选择晶体管，其结构是这两个晶体管串联连接。位线连接到选择晶体管的漏极区域，并且字线连接到其栅电极。单元晶体管的栅极电极不会在任何地方电连接，以便处于浮置电位状态，而其漏极区域连接到选择晶体管的源极区域。源极线连接到单元晶体管的源极区域。

95. 发明申请

US20060157801A1 Nonvolatile semiconductor memory device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20060157801A1
公开(公告)日：2006-07-20
申请号：US11302203
申请日：2005-12-14
申请人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
发明人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11543 , Y10S257/909
摘要： A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.
摘要翻译：一种非易失性半导体存储器件的制造方法，具有在存储单元部分的外围电路部分和第二栅电极上形成第一栅电极的步骤，将杂质引入外围电路部分和存储单元部分的步骤，在至少所述存储单元部分之上形成第一绝缘膜的步骤，以及对其中引入了所述杂质的所述半导体衬底进行退火的步骤。第一栅电极具有第一栅极长度。第二栅电极具有比第一栅极长度短的第二栅极长度。

96. 发明授权

US07078763B2 Nonvolatile semiconductor memory device including improved gate electrode 失效
公开(公告)号：US07078763B2
公开(公告)日：2006-07-18
申请号：US10648510
申请日：2003-08-27
申请人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma , Riichiro Shirota , Akira Shimizu
发明人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma , Riichiro Shirota , Akira Shimizu
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/7883
摘要： A floating gate is formed on a semiconductor substrate via a gate insulating film. Diffused layers are formed as sources or drain regions on opposite sides of the floating gate in the semiconductor substrate. First and second control gates are formed opposite to both of the diffused layers on the opposite sides of the floating gate via an inter-gate insulating film to drive the floating gate.

97. 发明申请

US20060152208A1 Time limit function utilization apparatus 有权
公开(公告)号：US20060152208A1
公开(公告)日：2006-07-13
申请号：US11353218
申请日：2006-02-14
申请人： Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
发明人： Hiroshi Watanabe , Kazuya Matsuzawa , Riichiro Shirota
IPC分类号： G01R19/00
CPC分类号： H01L29/7883 , G01R31/2642 , G06F9/3802 , G06F2221/2137 , G06K19/0723 , G06K19/073 , G06K19/07372 , G06Q20/341 , G07C9/00111 , G07C2009/00976 , G07F7/082 , G07F7/084 , G07F7/1008 , G11C16/14 , G11C16/349 , H01L21/28273 , H01L27/115 , H01L27/11558 , H01L29/42324 , H01L29/66825
摘要： A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.

98. 发明授权

US07031195B2 Nonvolatile semiconductor memory having a control gate driver transistor whose gate insulator thickness is greater than that of a select gate driver transistor 失效
标题翻译：具有栅极绝缘体厚度大于选择栅极驱动晶体管栅极绝缘体厚度的控制栅极驱动晶体管的非易失性半导体存储器
公开(公告)号：US07031195B2
公开(公告)日：2006-04-18
申请号：US10948295
申请日：2004-09-24
申请人： Atsuhiro Sato , Riichiro Shirota , Kikuko Sugimae , Koji Sakui
发明人： Atsuhiro Sato , Riichiro Shirota , Kikuko Sugimae , Koji Sakui
IPC分类号： G11C16/08
CPC分类号： G11C16/06 , G11C11/005 , G11C16/0433 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , H01L27/11521 , H01L27/11546
摘要： A nonvolatile semiconductor memory includes: a memory sub array including a memory cell unit configured with a memory cell transistor and a select transistor connected in series; a control gate line driver including a control gate line driver transistor connected to a control gate line of the memory cell transistor; and a select transistor gate line driver including a select gate line driver transistor connected to a select gate line of the select transistor. A thickness of a gate insulator of the control gate line driver transistor is thicker than that of the select gate line driver transistor.
摘要翻译：非易失性半导体存储器包括：存储器子阵列，包括配置有存储单元晶体管的存储单元单元和串联连接的选择晶体管; 控制栅极线驱动器，包括连接到存储单元晶体管的控制栅极线的控制栅极线驱动晶体管; 以及选择晶体管栅极线驱动器，其包括连接到选择晶体管的选择栅极线的选择栅极线驱动晶体管。控制栅极线驱动晶体管的栅极绝缘体的厚度比选择栅线驱动晶体管的厚度厚。

99. 发明申请

US20050265097A1 Nonvolatile semiconductor memory device 有权
公开(公告)号：US20050265097A1
公开(公告)日：2005-12-01
申请号：US11194799
申请日：2005-08-02
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C7/00 , G11C11/56 , G11C16/34
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit includes a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

100. 发明授权

US06878985B2 Nonvolatile semiconductor memory device having a memory cell that includes a floating gate electrode and control gate electrode 失效
标题翻译：具有包括浮置栅电极和控制栅电极的存储单元的非易失性半导体存储器件
公开(公告)号：US06878985B2
公开(公告)日：2005-04-12
申请号：US10382772
申请日：2003-03-07
申请人： Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Akira Shimizu , Yasuhiko Matsunaga , Masayuki Ichige , Hisataka Meguro
发明人： Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Akira Shimizu , Yasuhiko Matsunaga , Masayuki Ichige , Hisataka Meguro
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115
摘要： Element isolation insulating layers have an STI structure, and their upper surfaces are flat. A floating gate electrode is formed in a recess which is formed by projections of the element isolation insulating layers. The two opposing side surfaces of the floating gate electrode are covered with the element isolation insulating layers. The upper surface of the floating gate electrode is substantially leveled with the upper surfaces of the element isolation insulating layers. A gate insulating layer is formed on the floating gate electrode and element isolation insulating layers. The underlayer of this gate insulating layer is flat. A control gate electrode is formed on the gate insulating layer.
摘要翻译：元件隔离绝缘层具有STI结构，其上表面是平坦的。浮栅电极形成在由元件隔离绝缘层的突起形成的凹部中。浮置栅电极的两个相对的侧表面被元件隔离绝缘层覆盖。浮栅电极的上表面与元件隔离绝缘层的上表面基本平齐。在浮栅电极和元件隔离绝缘层上形成栅极绝缘层。该栅极绝缘层的底层是平坦的。在栅极绝缘层上形成控制栅电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式