专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US6166420A Method and structure of high and low K buried oxide for SoI technology 失效
标题翻译：用于SoI技术的高K和低K埋氧体的方法和结构
公开(公告)号：US6166420A
公开(公告)日：2000-12-26
申请号：US526369
申请日：2000-03-16
申请人： Robert J. Gauthier, Jr. , Dominic J. Schepis , Steven H. Voldman
发明人： Robert J. Gauthier, Jr. , Dominic J. Schepis , Steven H. Voldman
IPC分类号： H01L27/04 , H01L21/762 , H01L21/822 , H01L27/12 , H01L29/786 , H01L29/00 , H01L23/58
CPC分类号： H01L21/7624
摘要： A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions, depositing a first insulator over the substrate, patterning the first insulator such that the first insulator remains only over the first portion, depositing a second insulator over substrate (the first insulator has different thermal dissipation characteristics than the second insulator), polishing the second insulator to form a planar surface, and attaching a silicon film over the first insulator and the second insulator.
摘要翻译：用于形成集成电路晶片的方法和结构包括形成具有第一和第二部分的衬底，在衬底上沉积第一绝缘体，图案化第一绝缘体，使得第一绝缘体仅保留在第一部分之上，在衬底上沉积第二绝缘体（第一绝缘体具有与第二绝缘体不同的散热特性），抛光第二绝缘体以形成平坦表面，并且在第一绝缘体和第二绝缘体上附着硅膜。

92. 发明授权

US6100143A Method of making a depleted poly-silicon edged MOSFET structure 失效
标题翻译：制造耗尽多晶硅边缘MOSFET结构的方法
公开(公告)号：US6100143A
公开(公告)日：2000-08-08
申请号：US267239
申请日：1999-03-12
申请人： Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven H. Voldman
发明人： Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven H. Voldman
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L21/762 , H01L29/423 , H01L29/49 , H01L29/786
CPC分类号： H01L29/6659 , H01L21/28105 , H01L21/28123 , H01L21/76224 , H01L29/4238 , H01L29/4983 , Y10S438/919
摘要： A field effect transistor with reduced corner device problems comprises source and drain regions formed in a substrate, a channel region between the source and drain regions, isolation regions in the substrate adjacent the source, channel and drain regions; and a gate having a gate dopant over the channel region and separated therefrom by a gate dielectric. The isolation regions define corner regions of the channel along interfaces between the channel and isolation regions. The gate includes regions depleted of the gate dopant and overlapping at least the channel region and the isolation regions, such that voltage thresholds of the channel corner regions beneath depleted portions of the gate conductor layer are increased compared to regions of the channel between the corner regions.The field effect transistor with reduced dopant concentration on the MOSFET gate "corner" has an improved edge voltage tolerance. The structure has improved edge dielectric breakdown and lower MOSFET gate-induced drain leakage (GIDL). This structure is intended for analog applications, mixed voltage tolerant circuits and electrostatic (ESD) networks.
摘要翻译：具有减小的拐角设备问题的场效应晶体管包括形成在衬底中的源极和漏极区域，源极和漏极区域之间的沟道区域，邻近源极，沟道和漏极区域的衬底中的隔离区域; 以及在沟道区域上具有栅极掺杂剂并由栅极电介质分离的栅极。隔离区域定义了通道与隔离区域之间的接口的拐角区域。栅极包括耗尽栅极掺杂剂的区域，并且至少与沟道区域和隔离区域重叠，使得栅极导体层的耗尽部分之下的沟道拐角区域的电压阈值与角区域之间的沟道区域相比增加。 MOSFET栅极“拐角”上掺杂浓度降低的场效应晶体管具有改善的边缘电压容差。该结构具有改善的边缘电介质击穿和较低的MOSFET栅极引起的漏极泄漏（GIDL）。该结构适用于模拟应用，混合耐压电路和静电（ESD）网络。

93. 发明授权

US6033949A Method and structure to reduce latch-up using edge implants 失效
标题翻译：使用边缘植入物减少闭锁的方法和结构
公开(公告)号：US6033949A
公开(公告)日：2000-03-07
申请号：US107813
申请日：1998-06-30
申请人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
发明人： Faye D. Baker , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Steven J. Holmes , Robert K. Leidy , Edward J. Nowak , Steven H. Voldman
IPC分类号： H01L21/761 , G03F7/004 , H01L21/8238 , H01L27/08 , H01L27/092
CPC分类号： H01L21/823878 , H01L27/0921 , Y10S148/137
摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.
摘要翻译：本发明的优选实施例克服了现有技术的限制，并且提供了一种通过在阱边缘处形成植入物来增加CMOS器件的闩锁抗扰度的装置和方法。优选的方法使用混合抗蚀剂在N阱和/或P阱的边缘形成这些植入物。植入物减少了寄生晶体管中少数载流子的寿命，从而降低了寄生晶体管的增益。这降低了CMOS器件闭锁的倾向。优选实施例方法允许形成这些植入物，而不需要比现有技术方法更多的掩蔽步骤。此外，用于形成植入物的优选方法导致与孔的边缘自对准的植入物。

94. 发明授权

US07825003B2 Method of doping field-effect-transistors (FETs) with reduced stress/strain relaxation and resulting FET devices 有权
标题翻译：掺杂具有减小的应力/应变弛豫和所得FET器件的场效应晶体管（FET）的方法
公开(公告)号：US07825003B2
公开(公告)日：2010-11-02
申请号：US11768266
申请日：2007-06-26
申请人： Robert J. Gauthier, Jr. , Rajendran Krishnasamy
发明人： Robert J. Gauthier, Jr. , Rajendran Krishnasamy
IPC分类号： H01L21/76
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a FET transistor for an integrated circuit by the steps of forming recesses in a substrate on both sides of a gate on the substrate, halo/extension ion implanting into the recesses, and filling the recesses with embedded strained layers comprising dopants for in-situ doping of the source and drain of the transistor. The stress/strain relaxation of the resulting transistor is reduced.
摘要翻译：一种通过以下步骤制造用于集成电路的FET晶体管的方法：在基板的栅极的两侧的基板上形成凹槽，将卤素/延伸离子注入到凹部中，以及用包含掺杂剂的嵌入的应变层填充凹部，晶体管的源极和漏极的原位掺杂。所得晶体管的应力/应变松弛减小。

95. 发明授权

US07804124B2 Device structures for a memory cell of a non-volatile random access memory and design structures for a non-volatile random access memory 失效
标题翻译：用于非易失性随机存取存储器的存储器单元的装置结构和用于非易失性随机存取存储器的设计结构
公开(公告)号：US07804124B2
公开(公告)日：2010-09-28
申请号：US12118241
申请日：2008-05-09
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Yun Shi , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Yun Shi , William R. Tonti
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42324
摘要： Device and design structures for memory cells in a non-volatile random access memory (NVRAM). The device structure includes a semiconductor body in direct contact with the insulating layer, a control gate electrode, and a floating gate electrode in direct contact with the insulating layer. The semiconductor body includes a source, a drain, and a channel between the source and the drain. The floating gate electrode is juxtaposed with the channel of the semiconductor body and is disposed between the control gate electrode and the insulating layer. A first dielectric layer is disposed between the channel of the semiconductor body and the floating gate electrode. A second dielectric layer is disposed between the control gate electrode and the floating gate electrode.
摘要翻译：非易失性随机存取存储器（NVRAM）中存储单元的器件和设计结构。器件结构包括与绝缘层直接接触的半导体本体，控制栅电极和与绝缘层直接接触的浮栅电极。半导体本体包括源极，漏极以及源极和漏极之间的沟道。浮置栅电极与半导体本体的沟道并置并且设置在控制栅电极和绝缘层之间。第一电介质层设置在半导体本体的沟道和浮栅之间。第二介电层设置在控制栅电极和浮栅电极之间。

96. 发明授权

US07791105B2 Device structures for a high voltage junction field effect transistor manufactured using a hybrid orientation technology wafer and design structures for a high voltage integrated circuit 失效
标题翻译：使用混合取向技术晶圆制造的高压结场效应晶体管的器件结构和用于高压集成电路的设计结构
公开(公告)号：US07791105B2
公开(公告)日：2010-09-07
申请号：US12121286
申请日：2008-05-15
申请人： Renata Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Andreas D. Stricker
发明人： Renata Camillo-Castillo , Robert J. Gauthier, Jr. , Richard A. Phelps , Andreas D. Stricker
IPC分类号： H01L29/778
CPC分类号： H01L29/808 , H01L29/0692
摘要： Device structures for a high voltage junction field effect transistor and design structures for a high voltage integrated circuit. The device structure is manufactured using a hybrid orientation technology wafer with a first semiconductor layer with a first crystalline orientation, a second semiconductor layer with a second crystalline orientation, and an insulating layer between the first and second semiconductor layers. The device structure includes an epitaxial semiconductor region having the second crystalline orientation and first and second p-n junctions in the epitaxial semiconductor region. The epitaxial semiconductor region extends from the second semiconductor layer through the insulating layer and the first semiconductor layer toward a top surface of the first semiconductor layer. The first and second p-n junctions are arranged in depth within the epitaxial semiconductor region between the second semiconductor layer and the top surface of the first semiconductor layer.
摘要翻译：高压结场效应晶体管的器件结构和高压集成电路的设计结构。使用具有第一晶体取向的第一半导体层，具有第二晶体取向的第二半导体层和在第一和第二半导体层之间的绝缘层的混合定向技术晶片制造器件结构。器件结构包括具有第二晶体取向的外延半导体区域和外延半导体区域中的第一和第二p-n结。外延半导体区域从第二半导体层延伸穿过绝缘层和第一半导体层朝向第一半导体层的顶表面延伸。第一和第二p-n结在第二半导体层和第一半导体层的顶表面之间的外延半导体区域内被深入布置。

97. 发明授权

US07737498B2 Enhanced stress-retention silicon-on-insulator devices and methods of fabricating enhanced stress retention silicon-on-insulator devices 失效
标题翻译：增强的应力保持硅绝缘体上的器件和制造增强的应力保持硅绝缘体上的器件的方法
公开(公告)号：US07737498B2
公开(公告)日：2010-06-15
申请号：US12116237
申请日：2008-05-07
申请人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed Hickory Rankin , Robert R. Robison , William Robert Tonti
发明人： Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed Hickory Rankin , Robert R. Robison , William Robert Tonti
IPC分类号： H01L21/00 , H01L21/338
CPC分类号： H01L29/78654 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/66772 , H01L29/7833 , H01L29/7848 , H01L29/7849 , H01L29/78603
摘要： Field effect transistor and methods of fabricating field effect transistors. The field effect transistors includes: a semiconductor substrate; a silicon oxide layer on the substrate; a stiffening layer on the silicon oxide layer; a single crystal silicon layer on the stiffening layer; a source and a drain on opposite sides of a channel region of the silicon layer; a gate electrode over the channel region and a gate dielectric between the gate electrode and the channel region.
摘要翻译：场效应晶体管和制造场效应晶体管的方法。场效应晶体管包括：半导体衬底; 衬底上的氧化硅层; 氧化硅层上的加强层; 加强层上的单晶硅层; 在硅层的沟道区的相对侧上的源极和漏极; 沟道区上的栅极电极和栅电极和沟道区之间的栅极电介质。

98. 发明授权

US07648869B2 Method of fabricating semiconductor structures for latch-up suppression 失效
标题翻译：制造用于闭锁抑制的半导体结构的方法
公开(公告)号：US07648869B2
公开(公告)日：2010-01-19
申请号：US11330689
申请日：2006-01-12
申请人： Shunhua Thomas Chang , Toshiharu Furukawa , Robert J. Gauthier, Jr. , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
发明人： Shunhua Thomas Chang , Toshiharu Furukawa , Robert J. Gauthier, Jr. , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L27/0921 , H01L21/823878
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a first doped well formed in a substrate of semiconductor material, a second doped well formed in the substrate proximate to the first doped well, and a deep trench defined in the substrate. The deep trench includes sidewalls positioned between the first and second doped wells. A buried conductive region is defined in the semiconductor material bordering the base and the sidewalls of the deep trench. The buried conductive region intersects the first and second doped wells. The buried conductive region has a higher dopant concentration than the first and second doped wells. The buried conductive region may be formed by solid phase diffusion from a mobile dopant-containing material placed in the deep trench. After the buried conductive region is formed, the mobile dopant-containing material may optionally remain in the deep trench.
摘要翻译：用于抑制大量CMOS器件中的闩锁的半导体结构和方法。该结构包括在半导体材料的衬底中形成的第一掺杂阱，在衬底中形成的靠近第一掺杂阱的第二掺杂阱以及限定在衬底中的深沟槽。深沟槽包括位于第一和第二掺杂阱之间的侧壁。在与深沟槽的基底和侧壁相邻的半导体材料中限定掩埋导电区域。埋入的导电区域与第一和第二掺杂阱相交。掩埋导电区域具有比第一和第二掺杂阱更高的掺杂剂浓度。掩埋导电区域可以通过从放置在深沟槽中的含有移动掺杂剂的材料的固相扩散形成。在形成掩埋导电区域之后，含有移动掺杂剂的材料可以任选地保留在深沟槽中。

99. 发明授权

US07473970B2 Concurrent fin-fet and thick body device fabrication 有权
标题翻译：并发鳍和厚体器件制造
公开(公告)号：US07473970B2
公开(公告)日：2009-01-06
申请号：US11481120
申请日：2006-07-05
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.
摘要翻译：集成电路芯片和半导体结构。集成电路芯片包括：包含半导体台面和掺杂体接触的厚体器件; 以及在半导体台面的第一侧壁上的场效应晶体管，其中所述掺杂体接触在所述半导体台面的第二侧壁上，并且其中所述半导体台面设置在所述场效应晶体管和所述掺杂体接触之间。半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。

100. 发明授权

US07301210B2 Method and structure to process thick and thin fins and variable fin to fin spacing 有权
标题翻译：处理厚薄翅片和可变翅片翅片间距的方法和结构
公开(公告)号：US07301210B2
公开(公告)日：2007-11-27
申请号：US11306827
申请日：2006-01-12
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , William R. Tonti
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211
摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.
摘要翻译：公开了一种集成电路，其具有在相同基板上具有不同宽度和可变间隔的多个半导体散热片。形成电路的方法包括使用不同类型的心轴的侧壁图像转印过程。翅片厚度和翅片翅片间距由用于在心轴上形成氧化物侧壁的氧化工艺控制，更具体地，通过处理时间和使用固有的，氧化增强的和/或氧化抑制的心轴来控制。翅片厚度也通过使用与氧化物侧壁结合或代替氧化物侧壁的侧壁间隔来控制。具体地，单独的氧化物侧壁的图像，侧壁间隔物的图像和/或侧壁间隔物和氧化物侧壁的组合图像被转移到半导体层中以形成散热片。可以使用具有不同厚度和可变间隔的散热片来形成单个多鳍FET，或者替代地，各种单鳍和/或多鳍FET。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式