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91. 发明申请

US20130001789A1 INTERCONNECT STRUCTURE WITH IMPROVED DIELECTRIC LINE TO VIA ELECTROMIGRATION RESISTANT INTERFACIAL LAYER AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：具有改进的介电线的互连结构通过电阻接触层及其制造方法
公开(公告)号：US20130001789A1
公开(公告)日：2013-01-03
申请号：US13617060
申请日：2012-09-14
申请人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith K. H. Wong
发明人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith K. H. Wong
IPC分类号： H01L23/48
CPC分类号： H01L21/76843 , H01L21/76814 , H01L21/76849 , H01L21/7685 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.
摘要翻译：提供具有改善的电迁移阻力的互连结构，其包括存在于通孔开口底部的金属界面层（或金属合金层）。通孔开口位于第二电介质材料内，第二电介质材料位于包括嵌入其中的第一导电材料的第一电介质材料的顶部。存在于通孔开口底部的金属界面层（或金属合金层）位于埋在第一电介质内的下面的第一导电材料和嵌入在第二电介质材料内的第二导电材料之间。还提供了制造改进的电迁移电阻互连结构的方法。

92. 发明授权

US08288276B2 Method of forming an interconnect structure including a metallic interfacial layer located at a bottom via portion 有权
标题翻译：形成包括位于底部通孔部分的金属界面层的互连结构的方法
公开(公告)号：US08288276B2
公开(公告)日：2012-10-16
申请号：US12346040
申请日：2008-12-30
申请人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith Kwong Hon Wong
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76814 , H01L21/76849 , H01L21/7685 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.
摘要翻译：提供具有改善的电迁移阻力的互连结构，其包括存在于通孔开口底部的金属界面层（或金属合金层）。通孔开口位于第二电介质材料内，第二电介质材料位于包括嵌入其中的第一导电材料的第一电介质材料的顶部。存在于通孔开口底部的金属界面层（或金属合金层）位于埋在第一电介质内的下面的第一导电材料和嵌入在第二电介质材料内的第二导电材料之间。还提供了制造改进的电迁移电阻互连结构的方法。

93. 发明授权

US07768130B2 BEOL interconnect structures with simultaneous high-k and low-k dielectric regions 有权
标题翻译： BEOL互连结构，同时具有高k和低k电介质区域
公开(公告)号：US07768130B2
公开(公告)日：2010-08-03
申请号：US11939671
申请日：2007-11-14
申请人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L23/52
CPC分类号： H01L23/5329 , H01L21/7682 , H01L21/76849 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in the first ILD. The columnar air gap structure is created using a two-phase photoresist material for providing different etching selectivity during subsequent processing.
摘要翻译：一种用于制造和后端（BEOL）金属化结构的方法包括同时存在的高k和低k电介质区域。互连结构包括第一层间电介质（ILD）层和具有位于第二ILD层下面的第一ILD层的第二ILD层。在第一ILD中形成多个柱状气隙。使用两相光致抗蚀剂材料制造柱状气隙结构，用于在随后的处理期间提供不同的蚀刻选择性。

94. 发明申请

US20100164111A1 INTERCONNECT STRUCTURE WITH IMPROVED DIELECTRIC LINE TO VIA ELECTROMIGRATION RESISTANT INTERFACIAL LAYER AND METHOD OF FABRICATING SAME 有权
标题翻译：具有改进的介电线的互连结构通过电阻接触层及其制造方法
公开(公告)号：US20100164111A1
公开(公告)日：2010-07-01
申请号：US12346040
申请日：2008-12-30
申请人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith Kwong Hon Wong
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L21/76843 , H01L21/76814 , H01L21/76849 , H01L21/7685 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.
摘要翻译：提供具有改善的电迁移阻力的互连结构，其包括存在于通孔开口底部的金属界面层（或金属合金层）。通孔开口位于第二电介质材料内，第二电介质材料位于包括嵌入其中的第一导电材料的第一电介质材料的顶部。存在于通孔开口底部的金属界面层（或金属合金层）位于埋在第一电介质内的下面的第一导电材料和嵌入在第二电介质材料内的第二导电材料之间。还提供了制造改进的电迁移电阻互连结构的方法。

95. 发明授权

US07728371B2 SOI CMOS compatible multiplanar capacitor 有权
标题翻译： SOI CMOS兼容多平面电容器
公开(公告)号：US07728371B2
公开(公告)日：2010-06-01
申请号：US11857770
申请日：2007-09-19
申请人： Kangguo Cheng , Louis C Hsu , Jack A. Mandelman , William Tonti
发明人： Kangguo Cheng , Louis C Hsu , Jack A. Mandelman , William Tonti
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/10861 , H01L28/60
摘要： An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.
摘要翻译：孤立的浅沟槽隔离部分形成在绝缘体上半导体衬底的顶部半导体部分以及浅沟槽隔离结构中。环形形状的沟槽形成在掺杂顶部半导体部分周围，并填充有诸如掺杂多晶硅的导电材料。隔离的浅沟槽隔离部分和由导电材料的环限定的掩埋绝缘体层的部分被蚀刻以形成空腔。在空腔内的暴露的半导体表面上和掺杂的顶部半导体部分之上形成电容器电介质。形成在沟槽中并且在掺杂顶部半导体部分上方的导电材料部分构成电容器的内部电极，而导电材料的环，掺杂的顶部半导体部分和与电容器电介质邻接的手柄衬底的一部分构成一个第二电极。

96. 发明申请

US20080157202A1 SOFT ERROR REDUCTION OF CMOS CIRCUITS ON SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION USING BURIED RECOMBINATION CENTERS 有权
标题翻译：使用BURIED重组中心使用混合晶体方位的基板上CMOS电路的软错误减少
公开(公告)号：US20080157202A1
公开(公告)日：2008-07-03
申请号：US11618346
申请日：2006-12-29
申请人： Ethan H. Cannon , Toshiharu Furukawa , Charles Koburger , Jack A. Mandelman , William Tonti
发明人： Ethan H. Cannon , Toshiharu Furukawa , Charles Koburger , Jack A. Mandelman , William Tonti
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L29/1083
摘要： Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.
摘要翻译：公开了新的半导体结构和方法，用于通过在至少一个复合中心产生元件上植入至少一个复合中心产生元件以减少上述CMOS器件中的单一事件镦粗率来在混合取向技术的本体部分之下形成掩埋复合层。由复合中心产生元件引起的掩埋复合层中的晶体缺陷即使在高温退火之后也不会愈合，并且用作通过电离辐射产生的空穴和电子的复合中心。可以形成多个掩埋复合层。可选地，一个这样的层可以被正电压偏置以通过收集电子来阻止闭锁。

97. 发明授权

US07348280B2 Method for fabricating and BEOL interconnect structures with simultaneous formation of high-k and low-k dielectric regions 有权
标题翻译：同时形成高k和低k电介质区域的制造方法和BEOL互连结构
公开(公告)号：US07348280B2
公开(公告)日：2008-03-25
申请号：US11266741
申请日：2005-11-03
申请人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L21/469
CPC分类号： H01L23/5329 , H01L21/7682 , H01L21/76849 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in the first ILD. The columnar air gap structure is created using a two-phase photoresist material for providing different etching selectivity during subsequent processing.
摘要翻译：一种用于制造和后端（BEOL）金属化结构的方法包括同时存在的高k和低k电介质区域。互连结构包括第一层间电介质（ILD）层和具有位于第二ILD层下面的第一ILD层的第二ILD层。在第一ILD中形成多个柱状气隙。使用两相光致抗蚀剂材料制造柱状气隙结构，用于在随后的处理期间提供不同的蚀刻选择性。

98. 发明申请

US20080061817A1 Changing Chip Function Based on Fuse States 审中-公开
标题翻译：基于保险丝状态改变芯片功能
公开(公告)号：US20080061817A1
公开(公告)日：2008-03-13
申请号：US11928539
申请日：2007-10-30
申请人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
发明人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
IPC分类号： H03K19/00
CPC分类号： G06F17/5054 , G06F21/76
摘要： Systems, methods, and design structures whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
摘要翻译：可以在设备已经离开制造商的控制之后控制电子设备的特定特征的操作和/或访问的系统，方法和设计结构。可以基于存储在诸如电可编程融合（eFUSES）的非易失性存储元件中的值来提供操作和/或访问。

99. 发明申请

US20080059924A1 Design Structures Incorporating Interconnect Structures with Liner Repair Layers 有权
标题翻译：将连接结构与衬管修复层结合在一起的设计结构
公开(公告)号：US20080059924A1
公开(公告)日：2008-03-06
申请号：US11875345
申请日：2007-10-19
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： G06F17/50
CPC分类号： H01L23/53238 , H01L21/76814 , H01L21/76844 , H01L21/76846 , H01L21/76868 , H01L2924/0002 , H01L2924/00
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes an interconnect structure with a liner formed on roughened dielectric material in an insulating layer and a conformal liner repair layer bridging that breaches in the liner. The conformal liner repair layer is formed of a conductive material, such as a cobalt-containing material. The conformal liner repair layer may be particularly useful for repairing discontinuities in a conductive liner disposed on roughened dielectric material bordering the trenches and vias of damascene interconnect structures.
摘要翻译：用于设计，制造或测试设计的机器可读介质中体现的设计结构。该设计结构包括互连结构，其具有在绝缘层中的粗糙化介电材料上形成的衬垫和桥接该衬里中的破损的保形衬里修复层。保形衬里修复层由诸如含钴材料的导电材料形成。保形衬里修复层可能特别适用于修复布置在与镶嵌互连结构的沟槽和通孔相邻的粗糙化介电材料上的导电衬垫中的不连续性。

100. 发明申请

US20080050903A1 ELECTRICALLY PROGRAMMABLE FUSE STRUCTURES WITH NARROWED WIDTH REGIONS CONFIGURED TO ENHANCE CURRENT CROWDING AND METHODS OF FABRICATING THEREOF 失效
标题翻译：电气可编程的保险丝结构，具有配置为提高电流消耗的窄幅区域及其制作方法
公开(公告)号：US20080050903A1
公开(公告)日：2008-02-28
申请号：US11876942
申请日：2007-10-23
申请人： Roger BOOTH , Jack Mandelman , William Tonti
发明人： Roger BOOTH , Jack Mandelman , William Tonti
IPC分类号： H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.
摘要翻译：提出了电可编程熔丝结构及其制造方法，其中熔丝包括通过细长的熔丝元件互连的第一和第二端部。第一端子部分具有大于熔丝元件的最大宽度的最大宽度，并且熔丝包括第一端子部分和熔丝元件接合的变窄的宽度区域。狭窄宽度区域至少部分地延伸并包括第一端子部分的一部分。变窄区域中的第一端子部分的宽度小于第一端子部分的最大宽度，以增强其中的电流拥挤。在另一实施方式中，熔丝元件包括限制宽度区域，其中熔丝元件的宽度小于其最大宽度以增强其中的电流拥挤，并且受限宽度区域的长度小于熔丝元件的总长度。

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