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1. 发明申请

US20120187528A1 FINFET FUSE WITH ENHANCED CURRENT CROWDING 失效
标题翻译： FINFET保险丝与增强电流冲击
公开(公告)号：US20120187528A1
公开(公告)日：2012-07-26
申请号：US13011215
申请日：2011-01-21
申请人： Kangguo Cheng , Louis C. Hsu , William R. Tonti , Chih-Chao Yang
发明人： Kangguo Cheng , Louis C. Hsu , William R. Tonti , Chih-Chao Yang
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method forms an eFuse structure that has a pair of adjacent semiconducting fins projecting from the planar surface of a substrate (in a direction perpendicular to the planar surface). The fins have planar sidewalls (perpendicular to the planar surface of the substrate) and planar tops (parallel to the planar surface of the substrate). The tops are positioned at distal ends of the fins relative to the substrate. An insulating layer covers the tops and the sidewalls of the fins and covers an intervening substrate portion of the planar surface of the substrate located between the fins. A metal layer covers the insulating layer. A pair of conductive contacts are connected to the metal layer at locations where the metal layer is adjacent the top of the fins.
摘要翻译：一种方法形成eFuse结构，其具有从衬底的平面（垂直于平面的方向）突出的一对相邻半导体翅片。散热片具有平面侧壁（垂直于基板的平面）和平面顶部（平行于基板的平面）。顶部相对于基底定位在翅片的远端。绝缘层覆盖翅片的顶部和侧壁，并且覆盖位于翅片之间的衬底的平面表面的中间衬底部分。金属层覆盖绝缘层。在金属层邻近翅片顶部的位置处，一对导电触头连接到金属层。

2. 发明授权

US08027416B2 Structure for data communications systems 失效
标题翻译：数据通信系统的结构
公开(公告)号：US08027416B2
公开(公告)日：2011-09-27
申请号：US12043166
申请日：2008-03-06
申请人： James S. Mason , Louis C. Hsu , Phil J. Murfet , Gareth J. Nicholls
发明人： James S. Mason , Louis C. Hsu , Phil J. Murfet , Gareth J. Nicholls
IPC分类号： H04L27/08
CPC分类号： H04L25/063 , H04L25/0292
摘要： A machine-readable medium thereupon stored a design structure; the design structure includes a receiver for a data communications system. The receiver includes a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.
摘要翻译：机器可读介质存储设计结构; 该设计结构包括用于数据通信系统的接收器。接收机包括用于从数据信道接收数据信号的数据路径，数据路径包括自动增益控制（AGC）环路; 以及信号检测器，用于响应于在信道上的数据信号的检测超过阈值并且根据来自数据路径中的AGC循环的增益信息，产生指示数据信号的有效性的数据有效信号。

3. 发明授权

US07968944B2 Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof 有权
标题翻译：具有混合体厚度的FET的集成电路芯片及其制造方法
公开(公告)号：US07968944B2
公开(公告)日：2011-06-28
申请号：US12541641
申请日：2009-08-14
申请人： Rajiv V. Joshi , Louis C. Hsu , Oleg Gluschenkov
发明人： Rajiv V. Joshi , Louis C. Hsu , Oleg Gluschenkov
IPC分类号： H01L27/12 , H01L29/00
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/78654
摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.
摘要翻译：一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。

4. 发明授权

US07927995B2 Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application 有权
标题翻译：采用埋入导电层的特征，用于电抗保险丝应用的电介质
公开(公告)号：US07927995B2
公开(公告)日：2011-04-19
申请号：US12541502
申请日：2009-08-14
申请人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Nicholas C. Fuller , Louis C. Hsu
发明人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Nicholas C. Fuller , Louis C. Hsu
IPC分类号： H01L21/44
CPC分类号： H01L23/5252 , H01L21/76843 , H01L21/76844 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.
摘要翻译：提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。也可以通过增加局部温度来加速相邻互连之间的电阻的降低。

5. 发明授权

US07911025B2 Fuse/anti-fuse structure and methods of making and programming same 有权
标题翻译：保险丝/反熔丝结构及制作和编程方法相同
公开(公告)号：US07911025B2
公开(公告)日：2011-03-22
申请号：US12127080
申请日：2008-05-27
申请人： Louis C. Hsu , Rajiv V. Joshi , Jack Allan Mandelman , Chih-Chao Yang
发明人： Louis C. Hsu , Rajiv V. Joshi , Jack Allan Mandelman , Chih-Chao Yang
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.
摘要翻译：提供了用于熔丝/反熔丝结构的技术，包括内部导体结构，从内部导体结构向外间隔开的绝缘层，设置在绝缘层外部的外部导体结构，以及限定空腔的空腔限定结构，其中所述空腔限定结构的至少一部分由所述内部导体结构，所述绝缘层和所述外部导体结构中的至少一个形成。还提供了制造和编程保险丝/反熔丝结构的方法。

6. 发明授权

US07902061B2 Interconnect structures with encasing cap and methods of making thereof 有权
标题翻译：具有封盖的互连结构及其制造方法
公开(公告)号：US07902061B2
公开(公告)日：2011-03-08
申请号：US12199407
申请日：2008-08-27
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Theodorus E. Standaert , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Theodorus E. Standaert , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/2885 , H01L21/76885 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of making an interconnect structure: which includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric material; and depositing an encasing cap over the extended portion of the interconnect structure.
摘要翻译：一种制造互连结构的方法，其包括在介电材料中提供互连结构，使介电材料凹陷，使得互连结构的一部分在电介质材料的上表面上方延伸; 以及在所述互连结构的延伸部分上沉积封装盖。

7. 发明授权

US07732922B2 Simultaneous grain modulation for BEOL applications 失效
标题翻译： BEOL应用的同时粒度调制
公开(公告)号：US07732922B2
公开(公告)日：2010-06-08
申请号：US11970149
申请日：2008-01-07
申请人： Chih-Chao Yang , Louis C. Hsu , Rajiv V. Joshi
发明人： Chih-Chao Yang , Louis C. Hsu , Rajiv V. Joshi
IPC分类号： H01L29/40
CPC分类号： H01L23/53238 , H01L23/5226 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： The invention is directed to an improved semiconductor structure, such that within the same insulating layer, Cu interconnects embedded within the same insulating level layer have a different Cu grain size than other Cu interconnects embedded within the same insulating level layer.
摘要翻译：本发明涉及一种改进的半导体结构，使得在同一绝缘层内嵌入相同绝缘层的Cu互连件具有与嵌入在同一绝缘层中的其它Cu互连不同的Cu晶粒尺寸。

8. 发明授权

US07709365B2 CMOS well structure and method of forming the same 失效
标题翻译： CMOS阱结构及其形成方法
公开(公告)号：US07709365B2
公开(公告)日：2010-05-04
申请号：US11551959
申请日：2006-10-23
申请人： Wilfried Haensch , Terence B. Hook , Louis C. Hsu , Rajiv V. Joshi , Werner Rausch
发明人： Wilfried Haensch , Terence B. Hook , Louis C. Hsu , Rajiv V. Joshi , Werner Rausch
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L29/78 , H01L21/823892 , H01L27/0928
摘要： A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.
摘要翻译：一种用于形成CMOS阱结构的方法，包括在衬底上形成多个第一导电类型阱，所述多个第一导电类型阱中的每一个形成在第一掩模中的相应开口中。在每个第一导电类型的阱上形成盖，并且去除第一掩模。在每个第一导电类型的孔的侧壁上形成侧壁间隔物。形成多个第二导电型阱，多个第二导电型阱中的每一个形成在相应的第一导电型阱之间。在第一导电型阱和第二导电类型阱之间形成多个浅沟槽隔离。通过第一选择性外延生长工艺形成多个第一导电型阱，并且通过第二选择性外延生长工艺形成多个第二导电型阱。

9. 发明授权

US07651892B2 Electrical programmable metal resistor 失效
标题翻译：电气可编程金属电阻
公开(公告)号：US07651892B2
公开(公告)日：2010-01-26
申请号：US11535833
申请日：2006-09-27
申请人： Chih-Chao Yang , Lawrence A. Clevenger , James J. Demarest , Louis C. Hsu , Carl Radens
发明人： Chih-Chao Yang , Lawrence A. Clevenger , James J. Demarest , Louis C. Hsu , Carl Radens
IPC分类号： H01L21/20 , H01L21/82 , H01L21/44
CPC分类号： H01L23/5228 , H01L23/5256 , H01L23/5329 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides an electrical programmable metal resistor and a method of fabricating the same in which electromigration stress is used to create voids in the structure that increase the electrical resistance of the resistor. Specifically, a semiconductor structure is provided that includes an interconnect structure comprising at least one dielectric layer, wherein said at least one dielectric layer comprises at least two conductive regions and an overlying interconnect region embedded therein, said at least two conductive regions are in contact with said overlying interconnect region by at least two contacts and at least said interconnect region is separated from said at least one dielectric layer by a diffusion barrier, wherein voids are present in at least the interconnect region which increase the electrical resistance of the interconnect region.
摘要翻译：本发明提供一种电可编程金属电阻器及其制造方法，其中电迁移应力用于在结构中产生增加电阻器的电阻的空隙。具体而言，提供一种半导体结构，其包括包括至少一个电介质层的互连结构，其中所述至少一个电介质层包括至少两个导电区域和嵌入其中的覆盖互连区域，所述至少两个导电区域与所述覆盖互连区域由至少两个触点和至少所述互连区域通过扩散阻挡层与所述至少一个介电层分离，其中空隙存在于至少互连区域中，这增加了互连区域的电阻。

10. 发明申请

US20090212362A1 SOI FIELD EFFECT TRANSISTOR WITH A BACK GATE FOR MODULATING A FLOATING BODY 失效
标题翻译：具有用于调制浮动体的后盖的SOI场效应晶体管
公开(公告)号：US20090212362A1
公开(公告)日：2009-08-27
申请号：US12036325
申请日：2008-02-25
申请人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , Carl Radens , William Tonti
发明人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , Carl Radens , William Tonti
IPC分类号： H01L21/84 , H01L29/786
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66772 , H01L29/78612 , H01L29/78648
摘要： A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.
摘要翻译：将掩模层施加在顶部半导体层上并且被图案化以在开口中暴露浅沟槽隔离结构以及要在其中形成第一源极/漏极区域和主体的顶部半导体区域的一部分。将离子注入到开口区域内的埋入绝缘体层的一部分中以形成损坏的埋层绝缘体区域。去除浅沟槽隔离结构，并且损坏的埋层绝缘体区域被选择性地蚀刻到未损坏的埋入绝缘体部分以形成空腔。在顶部半导体区域的侧壁和暴露的底表面上形成介电层，并且形成填充空腔的背栅。形成接触以向后栅极提供电偏压，使得主体和第一源极/漏极区域的电势被电调制。

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