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1. 发明申请

US20130001789A1 INTERCONNECT STRUCTURE WITH IMPROVED DIELECTRIC LINE TO VIA ELECTROMIGRATION RESISTANT INTERFACIAL LAYER AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：具有改进的介电线的互连结构通过电阻接触层及其制造方法
公开(公告)号：US20130001789A1
公开(公告)日：2013-01-03
申请号：US13617060
申请日：2012-09-14
申请人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith K. H. Wong
发明人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith K. H. Wong
IPC分类号： H01L23/48
CPC分类号： H01L21/76843 , H01L21/76814 , H01L21/76849 , H01L21/7685 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.
摘要翻译：提供具有改善的电迁移阻力的互连结构，其包括存在于通孔开口底部的金属界面层（或金属合金层）。通孔开口位于第二电介质材料内，第二电介质材料位于包括嵌入其中的第一导电材料的第一电介质材料的顶部。存在于通孔开口底部的金属界面层（或金属合金层）位于埋在第一电介质内的下面的第一导电材料和嵌入在第二电介质材料内的第二导电材料之间。还提供了制造改进的电迁移电阻互连结构的方法。

2. 发明授权

US06887785B1 Etching openings of different depths using a single mask layer method and structure 失效
标题翻译：使用单一掩模层方法和结构蚀刻不同深度的开口
公开(公告)号：US06887785B1
公开(公告)日：2005-05-03
申请号：US10709564
申请日：2004-05-13
申请人： David M. Dobuzinsky , Carl J. Radens , Roy C. Iggulden , Jay W. Strane , Keith K. H. Wong
发明人： David M. Dobuzinsky , Carl J. Radens , Roy C. Iggulden , Jay W. Strane , Keith K. H. Wong
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76816 , H01L21/76831 , H01L21/76897
摘要： A semiconductor device with openings of differing depths in a substrate or layer is described, as are related methods for its manufacture. Through selective deposition of a single mask layer, whereby low aspect ratio openings are substantially coated while high aspect ratio are at most partially coated, subsequent etching of the substrate or layer is restricted to uncoated portions of the high aspect ratio openings. The result is a substrate or layer with openings of more than one depth using a single mask layer. In a second embodiment, the selective deposition of a single mask layer is utilized to etch a layer while protecting underlying structures from etching. In a third embodiment, the selective deposition of a single mask layer is utilized to etch an opening into a layer wherein the opening has a sub-lithographic diameter, i.e., the diameter of the opening is smaller than can be achieved with the particular lithographic technique employed.
摘要翻译：描述了在衬底或层中具有不同深度的开口的半导体器件，以及用于其制造的相关方法。通过选择性沉积单个掩模层，由此在高纵横比最多部分涂覆的同时基本上涂覆低纵横比的开口，随后对衬底或层的蚀刻被限制在高纵横比开口的未涂覆部分。结果是使用单个掩模层的具有多于一个深度的开口的基底或层。在第二实施例中，使用单个掩模层的选择性沉积来蚀刻层，同时保护下面的结构免受蚀刻。在第三实施例中，使用单个掩模层的选择性沉积来将开口蚀刻到其中开口具有亚光刻直径的开口，即，开口的直径小于可以用特定光刻技术实现的开口的直径雇用。

3. 发明授权

US08525232B2 Semiconductor structure having a wetting layer 有权
标题翻译：具有润湿层的半导体结构
公开(公告)号：US08525232B2
公开(公告)日：2013-09-03
申请号：US13206586
申请日：2011-08-10
申请人： Takeshi Nogami , Keith K. H. Wong , Chih-Chao Yang
发明人： Takeshi Nogami , Keith K. H. Wong , Chih-Chao Yang
IPC分类号： H01L29/78
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/32056 , H01L29/66545
摘要： A semiconductor structure which includes a semiconductor substrate and a metal gate structure formed in a trench or via on the semiconductor substrate. The metal gate structure includes a gate dielectric; a wetting layer selected from the group consisting of cobalt and nickel on the gate dielectric lining the trench or via and having an oxygen content of no more than about 200 ppm (parts per million) oxygen; and an aluminum layer to fill the remainder of the trench or via. There is also disclosed a method of forming a semiconductor structure in which a wetting layer is formed from cobalt amidinate or nickel amidinate deposited by a chemical vapor deposition process.
摘要翻译：一种半导体结构，其包括形成在半导体衬底上的沟槽或通孔中的半导体衬底和金属栅极结构。金属栅极结构包括栅极电介质; 选自钴和镍的润湿层，位于沟槽或通孔上的栅极电介质上，氧含量不超过约200ppm（百万分之一）氧; 以及铝层以填补沟槽或通孔的其余部分。还公开了一种形成半导体结构的方法，其中由通过化学气相沉积工艺沉积的脒化脒或脒化镍形成润湿层。

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