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    • 92. 发明授权
    • Transistor, semiconductor device and manufacturing method of semiconductor device
    • 晶体管,半导体器件及半导体器件的制造方法
    • US06746909B2
    • 2004-06-08
    • US10360815
    • 2003-02-10
    • Akira Nishiyama
    • Akira Nishiyama
    • H01I218238
    • H01L21/76897H01L21/28562H01L21/823835H01L21/823842H01L29/045H01L29/47H01L29/665H01L29/66545H01L29/66628H01L29/7834
    • A semiconductor device having a low channel resistance without degrading transistor characteristics even for the 0.1 &mgr;m generation or later, and also: a manufacturing method of the device. The method includes fabricating source/drain electrodes and a gate electrode without using selective metal growth methods. Further, after forming the gate electrode, a semiconductor film is temporarily formed selectively in source/drain regions. A dielectric film is next deposited on the substrate and then, the surface is etched by chemical/mechanical polish (CMP) techniques to the extent that the semiconductor film is exposed on the surface. The semiconductor film is then partly etched until its midway portion along the thickness is removed. Thereafter, a desired metal or silicide is deposited on the entire surface. Next, CMP etching is performed to form electrodes, while letting the electrodes reside on or over the source/drain semiconductor layers and a gate insulation layer.
    • 具有低通道电阻而不降低晶体管特性的半导体器件,即使是0.1μm产生或更迟,以及该器件的制造方法。 该方法包括在不使用选择性金属生长方法的情况下制造源/漏电极和栅电极。 此外,在形成栅电极之后,半导体膜在源极/漏极区域中暂时选择性地形成。 接着在衬底上沉积电介质膜,然后通过化学/机械抛光(CMP)技术对表面进行蚀刻,使得半导体膜暴露在表面上。 然后半导体膜被部分蚀刻,直到其沿着厚度的中间部分被去除。 此后,在整个表面上沉积所需的金属或硅化物。 接下来,进行CMP蚀刻以形成电极,同时使电极驻留在源极/漏极半导体层上或栅极绝缘层上方。
    • 93. 发明授权
    • MIS transistor having a large driving current and method for producing the same
    • 具有大驱动电流的MIS晶体管及其制造方法
    • US06690047B2
    • 2004-02-10
    • US10132175
    • 2002-04-26
    • Yukihito OowakiMizuki OnoMitsuhiro NoguchiDaisaburo TakashimaAkira Nishiyama
    • Yukihito OowakiMizuki OnoMitsuhiro NoguchiDaisaburo TakashimaAkira Nishiyama
    • H01L2976
    • H01L21/28185H01L21/28194H01L21/28202H01L29/513H01L29/517H01L29/518H01L29/66545H01L29/66621H01L29/78
    • In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.
    • 在MIS晶体管中,形成在半导体基板1上的源极/漏极区域(S / D扩散层)的上表面布置成比半导体衬底上的沟道平面更靠近栅电极,源极/漏极区域的顶表面 漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。 在该晶体管中,在半导体衬底的表面中选择性地形成沟槽,并且可以将沉积在沟槽中的多晶硅用作掩模,以形成用作源极/漏极区域的杂质扩散层,以层压并形成栅极绝缘膜 的高介电膜和栅电极。 或者,可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。 因此,可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。
    • 94. 发明授权
    • Sub-tenth micron misfet with source and drain layers formed over source and drains, sloping away from the gate
    • 次级十分之一误差,源极和漏极层形成在源极和漏极之间,远离栅极倾斜
    • US06548875B2
    • 2003-04-15
    • US09798924
    • 2001-03-06
    • Akira Nishiyama
    • Akira Nishiyama
    • H01L2978
    • H01L21/76897H01L21/28562H01L21/823835H01L21/823842H01L29/045H01L29/47H01L29/665H01L29/66545H01L29/66628H01L29/7834
    • A semiconductor device having a low channel resistance without degrading transistor characteristics even for the 0.1 &mgr;m generation or later, and also: a manufacturing method of the device. The method includes fabricating source/drain electrodes and a gate electrode without using selective metal growth methods. Further, after forming the gate electrode, a semiconductor film is temporarily formed selectively in source/drain regions. A dielectric film is next deposited on the substrate and then, the surface is etched by chemical/mechanical polish (CMP) techniques to the extent that the semiconductor film is exposed on the surface. The semiconductor film is then partly etched until its midway portion along the thickness is removed. Thereafter, a desired metal or silicide is deposited on the entire surface. Next, CMP etching is performed to form electrodes, while letting the electrodes reside on or over the source/drain semiconductor layers and a gate insulation layer.
    • 具有低通道电阻而不降低晶体管特性的半导体器件,即使是0.1μm产生或更迟,以及该器件的制造方法。 该方法包括在不使用选择性金属生长方法的情况下制造源/漏电极和栅电极。 此外,在形成栅电极之后,半导体膜在源极/漏极区域中暂时选择性地形成。 接着在衬底上沉积电介质膜,然后通过化学/机械抛光(CMP)技术对表面进行蚀刻,使得半导体膜暴露在表面上。 然后半导体膜被部分蚀刻,直到其沿着厚度的中间部分被去除。 此后,在整个表面上沉积所需的金属或硅化物。 接下来,进行CMP蚀刻以形成电极,同时使电极驻留在源极/漏极半导体层上或栅极绝缘层上方。
    • 96. 发明授权
    • Semiconductor device and a method of manufacturing the same
    • 半导体装置及其制造方法
    • US06207486B1
    • 2001-03-27
    • US09151401
    • 1998-09-11
    • Akira Nishiyama
    • Akira Nishiyama
    • H01L218238
    • H01L21/76823H01L21/28568H01L21/76843H01L21/76852H01L21/76855
    • An object of the present invention is to provide a semiconductor device manufacturing method capable of facilitating achievement of reliable electrical connections between an electrode and a wiring layer in different layers or between wiring layers therein. In accordance with one aspect of the present invention, a semiconductor device manufacturing method includes the steps of forming an element isolation region 51 on one main surface of a semiconductor substrate 50, forming a gate electrode 53, forming source and drain electrodes 56, forming an insulator nitride film 57 on the main surface of the semiconductor substrate 50, forming an interlayer insulator 58 with more than one contact hole H, converting part of the insulator nitride film 57 at the bottom of the contact hole H into a conductive nitride film 61 that is higher in bonding energy than the insulative nitride, and forming wiring layer 62 connected to the source/drain electrodes 56 through the conductive nitride film 61.
    • 本发明的一个目的是提供一种能够有助于实现电极和不同层之间或布线层之间的布线层之间的可靠电连接的半导体器件制造方法。根据本发明的一个方面,半导体 器件制造方法包括以下步骤:在半导体衬底50的一个主表面上形成元件隔离区域51,形成栅电极53,形成源极和漏电极56,在半导体衬底的主表面上形成绝缘体氮化物膜57 如图50所示,形成具有多于一个接触孔H的层间绝缘体58,将接触孔H的底部的绝缘体氮化物膜57的一部分转换为与绝缘氮化物结合能力高的导电氮化物膜61,并形成 通过导电氮化物膜61连接到源/漏电极56的布线层62。
    • 97. 发明授权
    • Video receiving apparatus and video receiving method
    • 视频接收装置和视频接收方法
    • US08401359B2
    • 2013-03-19
    • US11890298
    • 2007-08-03
    • Takuro ShojiAkira Nishiyama
    • Takuro ShojiAkira Nishiyama
    • H04N5/765H04N7/12H04N9/80H04N17/00H04N7/00H04N7/16H03M7/00H04J3/06H04L12/28
    • G09G5/006G09G2370/047H04N5/06H04N5/46H04N21/43632
    • A video receiving apparatus having an input terminal to receive pixel-based video data transmitted with pixel clock synchronized with the video data is provided. The video receiving apparatus may include a separation unit, an information acquisition unit, and a determination unit. The separation unit may be configured to separate auxiliary data added to the video data from the video data obtained at the input terminal. The information acquisition unit may be configured to acquire information on the number of horizontal pixels and the number of vertical pixels for the input video data from the auxiliary data separated at the separation unit. The determination unit may be configured to determine a type of the input video data based on the information on the number of horizontal pixels and the number of vertical pixels that is obtained at the information acquisition unit.
    • 提供具有输入端子以接收与视频数据同步的像素时钟发送的基于像素的视频数据的视频接收装置。 视频接收装置可以包括分离单元,信息获取单元和确定单元。 分离单元可以被配置为从在输入端获得的视频数据中分离添加到视频数据的辅助数据。 信息获取单元可以被配置为从在分离单元处分离的辅助数据获取关于输入视频数据的水平像素数和垂直像素数的信息。 确定单元可以被配置为基于关于在信息获取单元获得的水平像素的数量和垂直像素的数量的信息来确定输入视频数据的类型。
    • 98. 发明申请
    • Method for Production of Optically Active 3-Amino-Nitrogenated Compound
    • 光学活性3-氨基氮化合物的制备方法
    • US20090326246A1
    • 2009-12-31
    • US12375141
    • 2007-07-23
    • Masatoshi OhnukiMasashi IzumidaAkira NishiyamaShingo Matsumoto
    • Masatoshi OhnukiMasashi IzumidaAkira NishiyamaShingo Matsumoto
    • C07D207/04
    • C07D207/14C07D207/10C07D207/12C07D207/27
    • Aiming at production of an optically active 3-amino nitrogen-containing compound which is useful as an intermediate in synthesis of medicines and pesticides, in particular, an optically active 1-protected-3-aminopyrrolidine derivative, from an inexpensive and readily available raw material by a process which is efficient and can be practiced industrially, an optically active 3-amino nitrogen-containing compound is produced by performing a reaction of an optically active 3-substituted nitrogen-containing compound with ammonia, methylamine, ethylamine or dimethylamine in the presence of water. In addition, a 1-protected-3-aminopyrrolidine derivative is produced by performing a reaction of an optically active 1-protected-3-(sulfonyloxy)pyrrolidine derivative with ammonia, methylamine, ethylamine, or dimethylamine in the presence of methanol, ethanol, n-propanol, or isopropanol under a pressure of less than 30 barr.
    • 本发明涉及一种光学活性3-氨基含氮化合物的制备,其可用作药物和农药合成中的中间体,特别是光学活性的1-保护的3-氨基吡咯烷衍生物,由廉价且容易获得的原料 通过工业上有效且可以在工业上实践的方法,通过在存在下进行光学活性的3-取代的含氮化合物与氨,甲胺,乙胺或二甲胺的反应来制备光学活性的3-氨基含氮化合物 的水。 此外,通过在甲醇,乙醇,甲醇,乙醇等的存在下进行光学活性的1-保护的3-(磺酰氧基)吡咯烷衍生物与氨,甲胺,乙胺或二甲胺的反应来制备1-保护的3-氨基吡咯烷衍生物, 正丙醇或异丙醇,压力小于30巴。
    • 99. 发明授权
    • MIS transistor and method for producing same
    • MIS晶体管及其制造方法
    • US07303965B2
    • 2007-12-04
    • US09879208
    • 2001-06-13
    • Yukihito OowakiMizuki OnoMitsuhiro NoguchiDaisaburo TakashimaAkira Nishiyama
    • Yukihito OowakiMizuki OnoMitsuhiro NoguchiDaisaburo TakashimaAkira Nishiyama
    • H01L21/33H01L21/3205H01L31/00
    • H01L21/28185H01L21/28194H01L21/28202H01L29/513H01L29/517H01L29/518H01L29/66545H01L29/66621H01L29/78
    • In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.
    • 在MIS晶体管中,形成在半导体基板1上的源极/漏极区域(S / D扩散层)的上表面布置成比半导体衬底上的沟道平面更靠近栅电极,源极/漏极区域的顶表面 漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。 在该晶体管中,在半导体衬底的表面中选择性地形成沟槽,并且可以将沉积在沟槽中的多晶硅用作掩模,以形成用作源极/漏极区域的杂质扩散层,以层压并形成栅极绝缘膜 的高介电膜和栅电极。 或者,可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。 因此,可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。