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91. 发明申请

US20080038917A1 MULTILAYER HARDMASK SCHEME FOR DAMAGE-FREE DUAL DAMASCENE PROCESSING OF SiCOH DIELECTRICS 失效
公开(公告)号：US20080038917A1
公开(公告)日：2008-02-14
申请号：US11873936
申请日：2007-10-17
申请人： Timothy Dalton , Nicholas Fuller , Stephen Gates
发明人： Timothy Dalton , Nicholas Fuller , Stephen Gates
IPC分类号： H01L21/4763
CPC分类号： H01L21/0331 , H01L21/76811 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T428/12576 , Y10T428/12611 , Y10T428/31667 , H01L2924/00
摘要： Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.

92. 发明申请

US20070267698A1 DUAL WIRED INTEGRATED CIRCUIT CHIPS 有权
标题翻译：双线集成电路板
公开(公告)号：US20070267698A1
公开(公告)日：2007-11-22
申请号：US11774853
申请日：2007-07-09
申请人： Kerry Bernstein , Timothy Dalton , Jeffrey Gambino , Mark Jaffe , Paul Kartschoke , Anthony Stamper
发明人： Kerry Bernstein , Timothy Dalton , Jeffrey Gambino , Mark Jaffe , Paul Kartschoke , Anthony Stamper
IPC分类号： H01L27/088 , H01L21/84
CPC分类号： H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/522 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.
摘要翻译：具有相对侧的布线电平的半导体器件以及制造与相对侧的器件和布线电平接触的半导体结构的方法。该方法包括在绝缘体上硅衬底上制造器件，其中器件的第一接触和第一侧的第一接触处的布线电平，去除下硅层以暴露所述掩埋氧化物层，形成第二接触器件通过掩埋氧化物层形成掩埋氧化物层上方的布线电平到第二触点。

93. 发明申请

US20070253661A1 WAVEGUIDE POLARIZATION BEAM SPLITTERS AND METHOD OF FABRICATING A WAVEGUIDE WIRE-GRID POLARIZATION BEAM SPLITTER 有权
标题翻译：波导偏振光束分离器及波导波导极化分束器的制作方法
公开(公告)号：US20070253661A1
公开(公告)日：2007-11-01
申请号：US11415923
申请日：2006-05-01
申请人： Charles Black , Gian-Luca Bona , Timothy Dalton , Nicholas Fuller , Roland Germann , Maurice McGlashan-Powell , Chandrasekhar Narayan , Robert Sandstrom
发明人： Charles Black , Gian-Luca Bona , Timothy Dalton , Nicholas Fuller , Roland Germann , Maurice McGlashan-Powell , Chandrasekhar Narayan , Robert Sandstrom
IPC分类号： G02B6/27 , B29D11/00
CPC分类号： G02B6/126 , B29D11/00759 , G02B6/136 , G02B2006/1215
摘要： A method in effectuating the redirection of light which is propagated within a waveguide, and which eliminates the necessity for a bending of the waveguide, or the drawbacks encountered in directional changes in propagated light involving the need for sharp curves of essentially small-sized radii, which would resultingly lead to excessive losses in light. In this connection, the method relates to the fabricating and the provision of a wire-grid polarization beam splitter within an optical waveguide, which utilizes a diblock copolymer template to formulate the wire-grid.
摘要翻译：实现在波导内传播的光的重定向并且消除波导的弯曲的必要性的方法或者涉及需要基本上小的半径的尖锐曲线的传播光的方向性变化中遇到的缺点，这将导致轻微的过度损失。在这方面，该方法涉及在光波导内制造和提供线栅偏振分束器，其利用二嵌段共聚物模板来配制线栅。

94. 发明申请

US20070181974A1 PLANAR VERTICAL RESISTOR AND BOND PAD RESISTOR AND RELATED METHOD 有权
标题翻译：平面垂直电阻和焊盘电阻及相关方法
公开(公告)号：US20070181974A1
公开(公告)日：2007-08-09
申请号：US11307404
申请日：2006-02-06
申请人： Douglas Coolbaugh , Timothy Dalton , Daniel Edelstein , Ebenezer Eshun , Jeffrey Gambino , Kevin Petrarca , Anthony Stamper , Richard Volant
发明人： Douglas Coolbaugh , Timothy Dalton , Daniel Edelstein , Ebenezer Eshun , Jeffrey Gambino , Kevin Petrarca , Anthony Stamper , Richard Volant
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L28/20 , H01L23/5228 , H01L23/53238 , H01L23/53295 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.
摘要翻译：公开了避免半导体器件小型化的问题的电阻器及相关方法。在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。这两个实施方案可以单独使用或一起使用。还公开了用于产生电阻器的相关方法。

95. 发明申请

US20070143721A1 SYSTEM AND METHOD FOR PLASMA INDUCED MODIFICATION AND IMPROVEMENT OF CRITICAL DIMENSION UNIFORMITY 有权
标题翻译：等离子体诱导改性的系统与方法及关键尺寸均匀性的改进
公开(公告)号：US20070143721A1
公开(公告)日：2007-06-21
申请号：US11676674
申请日：2007-02-20
申请人： Timothy Dalton , Ronald Della Guardia , Nicholas Fuller
发明人： Timothy Dalton , Ronald Della Guardia , Nicholas Fuller
IPC分类号： G06F17/50
CPC分类号： H01L21/31138 , G03F7/40 , G03F7/405 , H01L21/0276 , H01L21/31144
摘要： Novel interconnect structures possessing a OSG or polymeric-based (90 nm and beyond BEOL technologies) in which advanced plasma processing is utilized to reduce post lithographic CD non-uniformity (“line edge roughness”) in semiconductor devices. The novel interconnect structure has enhanced liner and seed conformality and is therefore capable of delivering improved device performance, functionality and reliability.
摘要翻译：具有OSG或聚合物（90nm及以上的BEOL技术）的新型互连结构，其中采用先进的等离子体处理以减少半导体器件中的后平版印刷光盘不均匀性（“线边缘粗糙度”）。新颖的互连结构具有增强的衬垫和种子保形性，因此能够提供改进的设备性能，功能性和可靠性。

96. 发明申请

US20060105576A1 HIGH ION ENERGY AND REATIVE SPECIES PARTIAL PRESSURE PLASMA ASH PROCESS 有权
标题翻译：高离子能量和重要物质部分压力等离子体ASH过程
公开(公告)号：US20060105576A1
公开(公告)日：2006-05-18
申请号：US10904608
申请日：2004-11-18
申请人： Nicholas Fuller , Timothy Dalton
发明人： Nicholas Fuller , Timothy Dalton
IPC分类号： H01L21/00 , H01L21/84 , H01L21/302 , H01L21/461
CPC分类号： H01L21/76802 , G03F7/427 , H01L21/31138
摘要： A high ion energy and high pressure O2/CO-based plasma for ashing field photoresist material subsequent to via-level damascene processing. The optimized plasma ashing process is performed at greater than approximately 300 mT pressure and ion energy greater than approximately 500 W conditions with an oxygen partial pressure of greater than approximately 85%. The rapid ash rate of the high pressure/high ion energy process and minimal dissociation conditions (no “source” power is applied) allow minimal interaction between the interlevel dielectric and ash chemistry to achieve minimal overall sidewall modification of less than approximately 5 nm.
摘要翻译：用于经过层级镶嵌处理之后灰化场致光材料的高离子能量和高压O 2 2 / CO基等离子体。优化的等离子体灰化过程在大于约300mT的压力下进行，离子能量大于约500W条件，氧分压大于约85％。高压/高离子能量过程的快速灰分速率和最小解离条件（不施加“源”功率）允许层间电介质和灰分化学之间的最小相互作用，以实现小于约5nm的最小总体侧壁修饰。

97. 发明申请

US20050258542A1 Use of a porous dielectric material as an etch stop layer for non-porous dielectric films 有权
标题翻译：使用多孔电介质材料作为非多孔介电膜的蚀刻停止层
公开(公告)号：US20050258542A1
公开(公告)日：2005-11-24
申请号：US10845718
申请日：2004-05-14
申请人： Nicholas Fuller , Timothy Dalton
发明人： Nicholas Fuller , Timothy Dalton
IPC分类号： H01L21/768 , H01L23/48 , H01L23/532
CPC分类号： H01L21/76835 , H01L21/76807 , H01L21/76808 , H01L21/76829 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures possessing a non-porous (dense) low-k organosilicate glass (OSG) film utilizing a porous low-k OSG film as an etch stop layer or a porous low-k OSG film using a non-porous OSG film as a hardmask for use in semiconductor devices are provided herein. The novel interconnect structures are capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed and also because of the relatively uniform line heights made feasible by these unique and seemingly counterintuitive features. The present invention also provides a fluorocarbon-based dual damascene etch process that achieves selective etching of a dense low-k OSG films relative to that of a porous low-k OSG film owing to the tunability of the gas-phase fluorine:carbon ratio (gas dissociation) and ion current below a critical threshold and given the larger carbon content of the porous film relative to that of the dense film.
摘要翻译：具有使用多孔低k OSG膜作为蚀刻停止层的无孔（致密）低k有机硅酸盐玻璃（OSG）膜的互连结构或使用无孔OSG膜作为硬掩模的多孔低k OSG膜用于半导体器件中。新颖的互连结构能够提供改进的器件性能，功能和可靠性，这是由于与传统采用的叠层相比，堆叠的有效介电常数降低，并且还因为这些独特且看似违反直觉的特征使得线的高度相对均匀。本发明还提供了一种基于碳氟化合物的双镶嵌蚀刻工艺，由于气相氟：碳比的可调性，实现了相对于多孔低k OSG膜的致密低k OSG膜的选择性蚀刻（气体离解）和离子电流低于临界阈值，并且给出多孔膜相对于致密膜的碳含量较大。

98. 发明申请

US20050218504A1 FILLED CAVITIES SEMICONDUCTOR DEVICES 审中-公开
标题翻译：填充CAVITIES半导体器件
公开(公告)号：US20050218504A1
公开(公告)日：2005-10-06
申请号：US10708883
申请日：2004-03-30
申请人： Timothy Dalton , John Fitzsimmons , Anthony Stamper
发明人： Timothy Dalton , John Fitzsimmons , Anthony Stamper
IPC分类号： H01L21/311 , H01L21/316 , H01L21/768 , H01L23/14 , H01L23/522 , H01L23/532
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02271 , H01L21/31695 , H01L23/5222 , H01L23/5329 , H01L27/14636 , H01L2924/0002 , H01L2924/00
摘要： In an embodiment of the invention, a dielectric material comprises a matrix of a material selected from the group consisting essentially of organic materials, inorganic materials and organo-silicate materials; a plurality of pores dispersed throughout the matrix; and a gas filling the pores. The gas is selected from the group consisting essentially of inert gases, depositing gases, and breakdown suppressing gases. The filled pore dielectric material is suitably used in a damascene wiring layer. In further embodiments, a plasma device comprises an integrated circuit (IC) chip substrate; at least one dielectric layer having a thickness on a surface of the substrate, a cavity formed in the dielectric layer, at least two electrodes disposed in the cavity; and a plasma gas filling the cavity. The plasma device can operate as a light source or as a switch.
摘要翻译：在本发明的一个实施方案中，电介质材料包括选自基本上由有机材料，无机材料和有机硅酸盐材料组成的组的基体; 分散在整个基质中的多个孔; 和填充孔的气体。气体选自基本上由惰性气体，沉积气体和击穿抑制气体组成的组。填充孔介电材料适用于镶嵌布线层。在另外的实施例中，等离子体器件包括集成电路（IC）芯片衬底; 至少一个介电层，其具有在所述基板的表面上的厚度，在所述介电层中形成的空腔，设置在所述空腔中的至少两个电极; 以及填充空腔的等离子体气体。等离子体装置可以作为光源或开关操作。

99. 发明申请

US20050208742A1 OXIDIZED TANTALUM NITRIDE AS AN IMPROVED HARDMASK IN DUAL-DAMASCENE PROCESSING 审中-公开
标题翻译：氧化氮化钛作为双重加工过程中改进的硬质合金
公开(公告)号：US20050208742A1
公开(公告)日：2005-09-22
申请号：US10708648
申请日：2004-03-17
申请人： William America , Larry Clevenger , Andy Cowley , Timothy Dalton , Mark Hoinkis , Kaushik Kumar , Douglas La Tulipe
发明人： William America , Larry Clevenger , Andy Cowley , Timothy Dalton , Mark Hoinkis , Kaushik Kumar , Douglas La Tulipe
IPC分类号： H01L21/033 , H01L21/311 , H01L21/3205 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76811 , H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L21/76834
摘要： A method of producing an oxidized tantalum nitride (TaOxNx) hardmask layer for use in dual-damascene processing is described. Fine-line dual-damascene processing places competing, conflicting demands on the hardmask. Whereas critical dimension control needs a thicker hardmask, optical lithographic alignment is frustrated by the opacity of thick tantalum nitride (TaN). The technique solves the problem of TaN hardmask opacity with increasing thickness by oxidizing the TaN layer. Oxidation of the TaN hardmask increases the thickness of the hardmask to two to four times its original thickness and simultaneously increases its transparency by greater than ten times. This permits better CD control associated with a thicker hardmask while facilitating optical lithographic alignment.
摘要翻译：描述了用于双镶嵌加工的氧化氮化钽（TaO x N N N x S）硬掩模层的制造方法。精细的双镶嵌加工对硬掩模产生了竞争，冲突的要求。尽管临界尺寸控制需要较厚的硬掩模，但由于厚氮化钽（TaN）的不透明度，光学平版印刷对挫败感到沮丧。该技术通过氧化TaN层来解决厚度增加的TaN硬掩模不透明度问题。 TaN硬掩模的氧化将硬掩模的厚度增加到其原始厚度的两到四倍，同时将其透明度提高了十倍以上。这允许与更厚的硬掩模相关联的更好的CD控制，同时促进光学光刻对准。

100. 发明申请

US20050158985A1 Copper recess process with application to selective capping and electroless plating 有权
标题翻译：铜凹槽工艺，适用于选择性封盖和无电镀
公开(公告)号：US20050158985A1
公开(公告)日：2005-07-21
申请号：US11058783
申请日：2005-02-16
申请人： Shyng-Tsong Chen , Timothy Dalton , Kenneth Davis , Chao-Kun Hu , Fen Jamin , Steffen Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael Lofaro , Sandra Malhotra , Chandrasekhar Narayan , David Rath , Judith Rubino , Katherine Saenger , Andrew Simon , Sean Smith , Wei-tsu Tseng
发明人： Shyng-Tsong Chen , Timothy Dalton , Kenneth Davis , Chao-Kun Hu , Fen Jamin , Steffen Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael Lofaro , Sandra Malhotra , Chandrasekhar Narayan , David Rath , Judith Rubino , Katherine Saenger , Andrew Simon , Sean Smith , Wei-tsu Tseng
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44 , H01L21/4763 , H01L21/48
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76847 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.
摘要翻译：公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

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