专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US5770875A Large value capacitor for SOI 失效
标题翻译： SOI的大值电容器
公开(公告)号：US5770875A
公开(公告)日：1998-06-23
申请号：US724287
申请日：1996-09-16
申请人： Fariborz Assaderaghi , Louis L. Hsu , Jack A. Mandelman , William R. Tonti
发明人： Fariborz Assaderaghi , Louis L. Hsu , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L21/334 , H01L21/84 , H01L29/786 , H01L21/8242 , H01L27/108
CPC分类号： H01L29/66181 , H01L21/84
摘要： Large capacitance, low-impedance decoupling capacitors in SOI and their method of fabrication. A high conductivity trench substrate contact is made adjacent to the capacitor by removal of insulator lining the capacitor by use of an extra mask thereby making a substrate contact when the trench is filled with doped polysilicon. The inventive process is compatible with and easily integrated into existing SOI logic technologies. The SOI decoupling capacitors are formed in trenches which pass through the silicon and buried oxide layers and into the underlying silicon substrate.
摘要翻译： SOI中的大电容，低阻抗去耦电容及其制造方法。通过使用额外的掩模去除夹在电容器上的绝缘体，使与电容器相邻的高导电性沟槽衬底接触，从而当沟槽填充有掺杂多晶硅时进行衬底接触。本发明的方法与现有的SOI逻辑技术兼容并容易地集成。 SOI去耦电容器形成在通过硅和掩埋氧化物层并进入下面的硅衬底的沟槽中。

92. 发明授权

US5470681A Phase shift mask using liquid phase oxide deposition 失效
标题翻译：使用液相氧化物沉积的相移掩模
公开(公告)号：US5470681A
公开(公告)日：1995-11-28
申请号：US173394
申请日：1993-12-23
申请人： Timothy A. Brunner , Derek B. Dove , Louis L. Hsu
发明人： Timothy A. Brunner , Derek B. Dove , Louis L. Hsu
IPC分类号： G03F1/30 , H01L21/027 , G03F9/00
CPC分类号： G03F1/30
摘要： Selective deposition of silica from a liquid phase solution of silica in hydrofluorosilicic acid through openings in a pattern of polyimide or similar organic material provides an optically improved phase shift mask structure for making lithographic exposures since deposition can be made substantially anisotropic to yield deposits of substantially uniform thickness. Deposition from the liquid phase is readily controlled and highly predictable control of deposition rate can be achieved by control of temperature of a low temperature deposition process. Therefore the optical quality of the mask need not be compromised by other structures, such as etch stop layers, otherwise necessary to achieve high phase shift accuracy and the deposits of phase shift material are substantially homogeneous. The process of deposition from the liquid phase can be stopped and started at will and the mask can be fabricated by a process which is substantially free from material-dependent or material-based process restrictions. The index of refraction of the deposited material can also be adjusted by annealing.
摘要翻译：从二氧化硅的液相溶液中选择性沉积二氧化硅在氢氟硅酸中通过聚酰亚胺或类似有机材料图案的开口提供光学改进的相移掩模结构，用于制备平版印刷曝光，因为沉积可以基本上是各向异性的，以产生基本均匀的沉积物厚度。易于控制液相的沉积，可以通过控制低温沉积工艺的温度来实现沉积速率的高度可预测的控制。因此，掩模的光学质量不需要被其它结构（例如蚀刻停止层）所影响，否则为实现高相移精度而必需，并且相移材料的沉积基本上是均匀的。可以停止从液相沉积的过程并且随意开始，并且可以通过基本上不含材料依赖或基于材料的工艺限制的方法来制造掩模。沉积材料的折射率也可以通过退火进行调整。

93. 发明授权

US5426330A Refractory metal capped low resistivity metal conductor lines and vias 失效
$Refractory metal capped low resistivity metal conductor lines and vias$
标题翻译：耐火金属封盖的低电阻金属导线和通孔
公开(公告)号：US5426330A
公开(公告)日：1995-06-20
申请号：US125107
申请日：1993-09-21
申请人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
发明人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
IPC分类号： H01L21/28 , H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/498 , H01L23/522 , H01L23/532 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/76838 , H01L21/7684 , H01L21/76847 , H01L21/76849 , H01L21/76852 , H01L21/76877 , H01L23/49866 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/09701 , Y10S148/015 , Y10S257/915 , Y10S438/959
摘要： A device includes a substrate, at least one dielectric layer positioned on said substrate, and metalization positioned in an opening in the at least one dielectric layer and extending a predetermined distance towards the substrate from a surface which is substantially coplanar with a surface of the at least one dielectric layer. The metalization includes a low resistivity metal or alloy encapsulated by a refractory metal or alloy having a resistivity greater than that of the low resistivity metal or alloy and having a columnar structure. The metalization has a plurality of sides in cross-section, at least three sides of the plurality of sides being substantially formed of a refractory metal or alloy having a common composition, at least two sides of the plurality of sides extending substantially the predetermined distance, and all of the plurality of sides being formed within the opening in the at least one dielectric layer.
摘要翻译：一种器件包括衬底，位于所述衬底上的至少一个电介质层和位于所述至少一个介电层中的开口中的金属化，并且从与所述衬底的表面基本上共面的表面向所述衬底延伸预定距离至少一个介电层。金属化包括由难熔金属或合金包覆的低电阻率金属或合金，其电阻率大于低电阻率金属或合金的电阻率，并具有柱状结构。金属化具有多个横截面，多个侧面的至少三个边基本上由具有共同成分的难熔金属或合金形成，多个侧面的至少两侧基本上延伸预定距离，并且所述多个侧面中的所有多个侧面形成在所述至少一个介电层中的开口内。

94. 发明授权

US5405795A Method of forming a SOI transistor having a self-aligned body contact 失效
标题翻译：形成具有自对准体接触的SOI晶体管的方法
公开(公告)号：US5405795A
公开(公告)日：1995-04-11
申请号：US268380
申请日：1994-06-29
申请人： Klaus D. Beyer , Taqi N. Buti , Chang-Ming Hsieh , Louis L. Hsu
发明人： Klaus D. Beyer , Taqi N. Buti , Chang-Ming Hsieh , Louis L. Hsu
IPC分类号： H01L21/336 , H01L29/786 , H01L21/265
CPC分类号： H01L29/66772 , H01L29/41783 , H01L29/78612 , Y10S148/15
摘要： An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.
摘要翻译： SOI晶体管具有通过对门的延伸形成的自对准体接触，从而以最小的面积增加形成身体接触，并且还避免了将源连接到身体的需要，如通过身体的现有技术方案通过来源联系。身体接触孔通过提高源极和漏极以形成初始孔径而形成，沉积被蚀刻以形成孔限定侧壁的共形层并且使用这些侧壁蚀刻接触孔以限定支撑绝缘侧壁以隔离的侧壁支撑构件收集电极来自闸门和源极和漏极。

95. 发明授权

US5300813A Refractory metal capped low resistivity metal conductor lines and vias 失效
$Refractory metal capped low resistivity metal conductor lines and vias$
标题翻译：耐火金属封盖的低电阻金属导线和通孔
公开(公告)号：US5300813A
公开(公告)日：1994-04-05
申请号：US841967
申请日：1992-02-26
申请人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
发明人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
IPC分类号： H01L21/28 , H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/498 , H01L23/522 , H01L23/532 , H01L29/440 , H01L29/460
CPC分类号： H01L21/76843 , H01L21/76838 , H01L21/7684 , H01L21/76847 , H01L21/76849 , H01L21/76852 , H01L21/76877 , H01L23/49866 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/09701 , Y10S148/015 , Y10S257/915 , Y10S438/959
摘要： A contact structure for a semiconductor device having a first refractory metal layer formed only at the bottom of a contact hole. The first refractory metal is selected from a group comprising titanium (Ti), titanium alloys or compounds such as Ti/TiN, tungsten (W), titanium/tungsten (Ti/W) alloys, or chromium (Cr) or tantalum (Ta) and their alloys or some other suitable material. A low resistivity layer comprising a single, binary or ternary metalization is deposited over the first refractory metal layer in the contact hole by a method such as PVD using evaporation or collimated sputtering. The low resistivity layer has side walls which taper inwardly toward one another with increasing height of the layer and the low resistivity layer does not contact the side walls of the contact hole. The low resistivity layer may be Al.sub.x Cu.sub.y (x+y=1; x.gtoreq.0, y.gtoreq.0), ternary alloys such as Al-Pd-Cu or multicomponent alloys such as Al-Pd-Nb-Au. A second refractory metal layer is deposited over the low resistivity layer. The second refractory metal layer may be tungsten, cobalt, nickel, molybdenum or alloys/compounds such as Ti/TiN. The first and second refractory metal layers completely encapsulate the low resistivity layer. The first and second refractory metal layers can comprise an alloy containing silicon with a higher incorporated silicon content near the top of the contact hold present as a distinct or graded composition than at a location closer to the bottom of the contact hole.
摘要翻译：一种用于半导体器件的接触结构，其具有仅在接触孔的底部形成的第一难熔金属层。第一难熔金属选自钛（Ti），钛合金或Ti / TiN，钨（W），钛/钨（Ti / W）合金或铬（Cr）或钽（Ta）及其合金或其他合适的材料。包含单一二元或三元金属化的低电阻率层通过诸如使用蒸发或准直溅射的PVD的方法沉积在接触孔中的第一难熔金属层上。低电阻率层具有随着层的高度逐渐向内逐渐向内逐渐变细的侧壁，低电阻层不接触接触孔的侧壁。低电阻率层可以是AlxCuy（x + y = 1; x> = 0，y> = 0），诸如Al-Pd-Cu的三元合金或诸如Al-Pd-Nb-Au的多组分合金。在低电阻率层上沉积第二难熔金属层。第二耐火金属层可以是钨，钴，镍，钼或诸如Ti / TiN的合金/化合物。第一和第二难熔金属层完全封装低电阻率层。第一和第二难熔金属层可以包含含有硅的合金，其中接合保持层的顶部附近具有更高的掺入硅含量，作为不同或分级的组成，而不是靠近接触孔底部的位置。

96. 发明授权

US5270234A Deep submicron transistor fabrication method 失效
标题翻译：深亚微米晶体管制造方法
公开(公告)号：US5270234A
公开(公告)日：1993-12-14
申请号：US968788
申请日：1992-10-30
申请人： Daniel L. Huang , Louis L. Hsu , Wen-Yuan Wang
发明人： Daniel L. Huang , Louis L. Hsu , Wen-Yuan Wang
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66583 , H01L29/66537 , H01L29/78 , Y10S148/113
摘要： A deep submicron transistor fabrication method that employs only optical lithography involves the formation of a relatively wide aperture using optical techniques; the formation of composite sidewalls having differential etch resistance in the aperture to define a final aperture width less than that available with conventional optical techniques; the etching of the final aperture to expose a controlled channel length; the implantation of the channel through the aperture; and the implantation of source and drain with the sidewalls protecting previously doped LDD regions in the active area.
摘要翻译：仅使用光学光刻的深亚微米晶体管制造方法涉及使用光学技术形成相对较宽的孔径; 在孔中形成具有差的耐蚀刻性的复合侧壁以限定最小孔径宽度小于常规光学技术可获得的最小孔径宽度; 蚀刻最终孔径以暴露受控的通道长度; 通过孔径注入通道; 以及源极和漏极的注入，其侧壁保护有源区域中预先掺杂的LDD区域。

97. 发明授权

US5258640A Gate controlled Schottky barrier diode 失效
标题翻译：门控肖特基势垒二极管
公开(公告)号：US5258640A
公开(公告)日：1993-11-02
申请号：US939214
申请日：1992-09-02
申请人： Chang-Ming Hsieh , Louis L. Hsu , Phung T. Nguyen , Lawrence F. Wagner, Jr.
发明人： Chang-Ming Hsieh , Louis L. Hsu , Phung T. Nguyen , Lawrence F. Wagner, Jr.
IPC分类号： H01L29/739 , H01L29/48 , H01L29/56
CPC分类号： H01L29/7391
摘要： An integrated gate and semiconductor barrier layer diode which functions as a regular diode when the gate is turned off and as, a Schottky barrier diode with the gate turned on.
摘要翻译：集成栅极和半导体势垒层二极管，当栅极截止时用作正常二极管，并且作为肖特基势垒二极管导通。

98. 发明授权

US08450205B2 Redundancy design with electro-migration immunity and method of manufacture 失效
标题翻译：具有电迁移免疫力的冗余设计和制造方法
公开(公告)号：US08450205B2
公开(公告)日：2013-05-28
申请号：US13474244
申请日：2012-05-17
申请人： Louis L. Hsu , Conal E. Murray , Ping-Chuan Wang , Chih-Chao Yang
发明人： Louis L. Hsu , Conal E. Murray , Ping-Chuan Wang , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76838 , H01L21/76847 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.
摘要翻译：提供了基本上不受电迁移（EM）损害的高直流（DC）的IC互连以及IC互连的制造方法。一种结构包括层间电线之间的交叉处的通孔簇结构。通孔结构包括多个通孔，每个通孔填充有金属并衬有衬垫材料。至少两个相邻的通孔彼此接触并且多个通孔降低了层间电线之间的电流负载。

99. 发明授权

US08351166B2 Leakage sensor and switch device for deep-trench capacitor array 有权
标题翻译：泄漏传感器和开关器件用于深沟槽电容阵列
公开(公告)号：US08351166B2
公开(公告)日：2013-01-08
申请号：US12508665
申请日：2009-07-24
申请人： Howard H. Chen , Kai D. Feng , Louis L. Hsu , Seongwon Kim
发明人： Howard H. Chen , Kai D. Feng , Louis L. Hsu , Seongwon Kim
IPC分类号： H01G7/16 , G01R31/12
CPC分类号： G01R31/024 , G01R31/028
摘要： A high-density deep trench capacitor array with a plurality of leakage sensors and switch devices. Each capacitor array further comprises a plurality of sub-arrays, wherein the leakage in each sub-array is independently controlled by a sensor and switch unit. The leakage sensor comprises a current mirror, a transimpedance amplifier, a voltage comparator, and a timer. If excessive leakage current is detected, the switch unit will automatically disconnect the leaky capacitor module to reduce stand-by power and improve yield. An optional solid-state resistor can be formed on top of the deep trench capacitor array to increase the temperature and speed up the leakage screening process.
摘要翻译：一种高密度深沟槽电容阵列，具有多个漏电传感器和开关器件。每个电容器阵列还包括多个子阵列，其中每个子阵列中的泄漏由传感器和开关单元独立地控制。泄漏传感器包括电流镜，跨阻放大器，电压比较器和定时器。如果检测到过大的漏电流，开关单元将自动断开泄漏电容器模块，以降低待机功率并提高产量。可以在深沟槽电容器阵列的顶部形成可选的固态电阻器，以增加温度并加快泄漏检测过程。

100. 发明授权

US08324102B2 Techniques for impeding reverse engineering 有权
标题翻译：阻止逆向工程的技术
公开(公告)号：US08324102B2
公开(公告)日：2012-12-04
申请号：US13169248
申请日：2011-06-27
申请人： Louis L. Hsu , Rajiv V. Joshi , David W. Kruger
发明人： Louis L. Hsu , Rajiv V. Joshi , David W. Kruger
IPC分类号： H01L21/00
CPC分类号： H01L21/76816 , H01L21/76825 , H01L21/76831 , H01L21/76834 , H01L23/573 , H01L27/02 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.
摘要翻译：提供了反逆向工程技术。一方面，提供了一种在绝缘层中形成至少一个特征的方法。该方法包括以下步骤。离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同在植入区域外侧。空隙填充有至少一种导体材料以在绝缘层中形成特征。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式