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91. 发明申请

US20080313590A1 METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGRATED CIRCUIT 有权
标题翻译：用于评估集成电路中的时序的方法和系统
公开(公告)号：US20080313590A1
公开(公告)日：2008-12-18
申请号：US12183549
申请日：2008-07-31
申请人： Eric A. FOREMAN , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Eric A. FOREMAN , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G01R31/3016
摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.
摘要翻译：用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。

92. 发明申请

US20080270962A1 STATIC TIMING SLACKS ANALYSIS AND MODIFICATION 有权
标题翻译：静态时序分析与修改
公开(公告)号：US20080270962A1
公开(公告)日：2008-10-30
申请号：US12138871
申请日：2008-06-13
申请人： Thomas B. Chadwick , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wempie
发明人： Thomas B. Chadwick , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wempie
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.
摘要翻译：公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。

93. 发明申请

US20080201683A1 Method of Generating Wiring Routes with Matching Delay in the Presence of Process Variation 有权
公开(公告)号：US20080201683A1
公开(公告)日：2008-08-21
申请号：US12108629
申请日：2008-04-24
申请人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

94. 发明授权

US07398491B2 Method for fast incremental calculation of an impact of coupled noise on timing 有权
标题翻译：耦合噪声对定时影响的快速增量计算方法
公开(公告)号：US07398491B2
公开(公告)日：2008-07-08
申请号：US11420529
申请日：2006-05-26
申请人： Gregory M. Schaeffer , Alexander J. Suess , David J. Hathaway
发明人： Gregory M. Schaeffer , Alexander J. Suess , David J. Hathaway
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036
摘要： A method for incrementally calculating the impact of coupling noise on the timing of an integrated circuit (IC) having a plurality of logic stages by performing an initial timing analysis on the IC to provide a first determination of the impact of coupling noise on the timing. One or more design changes to the IC are then performed. In response to the design change, the impact of the coupling noise to the timing is calculated on the logic stage where the change was made and on the logic stages downstream thereof. The results of the calculations are then inputted to a timing analysis tool to adjust the delay and slew of each logic stage where the design change was made and to the logic stages downstream thereof.
摘要翻译：一种用于通过对IC执行初始定时分析来递增地计算耦合噪声对具有多个逻辑级的集成电路（IC）的定时的影响的方法，以提供耦合噪声对定时的影响的第一确定。然后执行对IC的一个或多个设计更改。响应于设计变化，耦合噪声对定时的影响是在进行改变的逻辑阶段和下游的逻辑级上计算的。然后将计算结果输入到定时分析工具，以调整进行设计更改的每个逻辑级的延迟和转换以及其下游的逻辑级。

95. 发明授权

US07346875B2 Wiring optimizations for power 有权
标题翻译：电力接线优化
公开(公告)号：US07346875B2
公开(公告)日：2008-03-18
申请号：US11176712
申请日：2005-07-07
申请人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5022 , G06F17/5077
摘要： An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.
摘要翻译：电气布线结构及其设计方法。该方法识别具有第一线和第二线的至少一个线对。第二根线已经是三态的，也可以是三态的。线对可以具有不小于预定或用户选择的最小相同方向切换概率的每时钟周期的相同方向的切换概率。或者，线对可以具有不小于预定或用户选择的最小相反方向切换概率的每时钟周期的相反方向切换概率。第一线和第二线满足至少一个数学关系，涉及：第一线和第二线之间的间隔; 以及第一线和第二线的公共行程长度。

96. 发明授权

US07325210B2 Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect 有权
标题翻译：混合线性线模型方法来调整具有RC互连的电路的晶体管宽度
公开(公告)号：US07325210B2
公开(公告)日：2008-01-29
申请号：US11077043
申请日：2005-03-10
申请人： Vasant Rao , Cindy Washburn , Jun Zhou , Jeffrey P. Soreff , Patrick M. Williams , David J. Hathaway
发明人： Vasant Rao , Cindy Washburn , Jun Zhou , Jeffrey P. Soreff , Patrick M. Williams , David J. Hathaway
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F17/5068
摘要： A hybrid linear wire model for tuning the transistor widths of circuits linked by RC interconnects is described. The method uses two embedded simulators during the tuning process on netlists that contain resistors (Rs). A Timing oriented simulator is used only for timing purposes on the original netlist that includes all the Rs. A Gradient oriented simulator is then run only on the modified netlist with all Rs shorted and within the iterative loop of the tuner to compute gradients. The present hybrid method achieves a significant improvement in computational speed. The Timing oriented simulator is fast and accurate for only timing netlists with Rs, but cannot compute gradients efficiently. The Gradient oriented simulator computes gradients efficiently but cannot do so in the presence of Rs. To prevent “de-tuning” that typically occurs when all Rs are shorted, ‘wire-adjusts’ are provided that make the initial timing results using the Gradient oriented simulator on the shorted netlist match the timing results using Timing oriented simulator on the original netlist. This permits the optimizer sense initially the correct set of critical timing paths, and more significantly, it permits the wire-adjusts keep track of the changing transistor widths to guide the optimizer during the iterations until convergence is achieved.
摘要翻译：描述了用于调谐由RC互连链接的电路的晶体管宽度的混合线性线模型。在调谐过程中，该方法使用两个嵌入式模拟器，其中包含电阻（Rs）。面向计时的模拟器仅用于包含所有Rs的原始网表的时序目的。然后，一个面向梯度的模拟器仅在修改后的网表上运行，所有的Rs都已经短路，并在调谐器的迭代循环内计算梯度。目前的混合方法实现了计算速度的显着提高。面向时序的模拟器只需要具有Rs的时间网络列表即可快速准确，但无法有效地计算渐变。梯度导向模拟器有效地计算梯度，但在Rs的存在下不能这样做。为了防止所有Rs短路时通常发生的“去调谐”，提供“线调整”，使得在短路网表上使用面向梯度的模拟器的初始定时结果与使用定时模型的原始网表上的定时结果相匹配。这允许优化器最初感测正确的关键定时路径集合，并且更重要的是，它允许线路调整跟踪改变的晶体管宽度，以在迭代期间引导优化器直到实现收敛。

97. 发明授权

US07135907B2 Clock signal distribution utilizing differential sinusoidal signal pair 失效
公开(公告)号：US07135907B2
公开(公告)日：2006-11-14
申请号：US11255707
申请日：2005-10-21
申请人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
发明人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.

98. 发明授权

US07071757B2 Clock signal distribution utilizing differential sinusoidal signal pair 有权
公开(公告)号：US07071757B2
公开(公告)日：2006-07-04
申请号：US09682473
申请日：2001-09-06
申请人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
发明人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.

99. 发明授权

US06826733B2 Parameter variation tolerant method for circuit design optimization 有权
标题翻译：电路设计优化的参数变化容限方法
公开(公告)号：US06826733B2
公开(公告)日：2004-11-30
申请号：US10159921
申请日：2002-05-30
申请人： David J. Hathaway , Xiaoliang Bai , Chandramouli Visweswariah , Philip N. Strenski
发明人： David J. Hathaway , Xiaoliang Bai , Chandramouli Visweswariah , Philip N. Strenski
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A method for optimizing the design of a chip or system by decreasing the cost function that encompasses a plurality of constraints in the presence of variations in the design parameters is described. The method makes use of numerical optimization, simulated annealing, or any other objective-driven optimization means, and accounts for uncertainties in the modeling of the design variables and functions. A significant reduction in the number of design constraints which are violated at the end of an optimization process is achieved, even when all the design constraints cannot be satisfied. The optimization also reduces the cycle time at which the design operates and limits the increase in the minimum operational cycle time of a particular implementation in the presence of variations that cannot be modeled or unpredictable variations in delay introduced by elements of the design. The method for optimizing the design includes the steps of: defining an objective function computed from variables and functions of the design of the chip or system; deriving a merit function from the objective function by adding to it a plurality of separation terms; and minimizing the merit function which reduces the expected value of the objective function when confronted with significant variations of the design variables and functions.
摘要翻译：描述了通过在存在设计参数的变化的情况下降低包含多个约束的成本函数来优化芯片或系统的设计的方法。该方法利用数值优化，模拟退火或任何其他目标驱动的优化手段，并考虑了设计变量和功能建模中的不确定性。即使在不能满足所有设计限制的情况下，也可以在优化过程结束时，大大减少设计限制的数量。该优化还减少了设计操作的周期时间，并且在存在不能被设计的元件引入的延迟不可模拟或不可预测的变化的变化的情况下限制特定实现的最小操作周期时间的增加。用于优化设计的方法包括以下步骤：定义从芯片或系统的设计的变量和功能计算的目标函数; 通过向目标函数中加入多个分离项，从而得出优点函数; 并且在面对设计变量和功能的显着变化时，最小化功能降低了目标函数的期望值。

100. 发明授权

US06792582B1 Concurrent logical and physical construction of voltage islands for mixed supply voltage designs 失效
标题翻译：用于混合电源电压设计的并联电压岛的逻辑和物理构造
公开(公告)号：US06792582B1
公开(公告)日：2004-09-14
申请号：US09713829
申请日：2000-11-15
申请人： John M Cohn , Alvar A. Dean , David J. Hathaway , David E. Lackey , Thomas M. Lepsic , Susan K. Lichtensteiger , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John M Cohn , Alvar A. Dean , David J. Hathaway , David E. Lackey , Thomas M. Lepsic , Susan K. Lichtensteiger , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5068
摘要： Both logical and physical construction of voltage islands is disclosed. A semiconductor chip design is partitioned into “bins”, which are areas of the design. In this way, a semiconductor chip design may be “sliced” into various areas and the areas may then be assigned to various voltage levels. Each bin may be thought of as a voltage island. Circuits in the design can be added to or removed from the various bins, thereby increasing or decreasing the speed and power of the circuits: the speed and power increase if a circuit is placed into a bin assigned a higher voltage, and the speed and power decrease if a circuit is placed into a bin having a lower voltage. The size and location of the bins may also be changed. By iterating these steps, the optimum power consumption may be met while still meeting speed constraints and other criteria. The present invention is applicable to any placement environment, such as an annealing placement tool, that proceeds through successive refinement of the locations of the circuits on the design and in which the placement process may be interrupted to make changes in placement of the logic.
摘要翻译：公开了电压岛的逻辑和物理结构。半导体芯片设计被划分为“箱”，这是设计的区域。以这种方式，可以将半导体芯片设计“切片”成各种区域，然后将这些区域分配给各种电压电平。每个仓可以被认为是电压岛。设计中的电路可以添加到各个机箱中或从各个机箱中移除，从而增加或减少电路的速度和功率：如果将电路放入分配较高电压的箱体中，速度和功率会增加，速度和功率如果将电路放置在具有较低电压的箱中，则减小。还可以改变箱子的大小和位置。通过迭代这些步骤，可以在满足速度限制和其他标准的同时满足最佳功耗。本发明可应用于诸如退火放置工具的任何放置环境，其通过连续细化设计上的电路的位置并且其中可以中断放置过程以使逻辑的放置变化。

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