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91. 发明授权

US07533282B2 Logic circuit apparatus for selectively assigning a plurality of circuit data to a plurality of programmable logic circuits for minimizing total power while maintaining necessary processing performance 失效
标题翻译：用于选择性地将多个电路数据分配给多个可编程逻辑电路以最小化总功率同时保持必要的处理性能的逻辑电路装置
公开(公告)号：US07533282B2
公开(公告)日：2009-05-12
申请号：US11949072
申请日：2007-12-03
申请人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto , Riku Ogawa
发明人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto , Riku Ogawa
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A logic circuit apparatus includes a plurality of programmable logic circuits, a circuit data memory, a control unit. The plurality of programmable logic circuits are each configured to have a changeable circuit component based on circuit data. Each programmable logic circuit has a different processing performance. The circuit data memory is used to store a plurality of circuit data and performance requirements for the circuit data. The control unit is configured to selectively assign the plurality of circuit data to the plurality of programmable logic circuits so that a total power of all programmable logic circuits minimizes on condition that the performance requirement of the circuit data assigned to each programmable logic circuit is within the processing performance of each programmable logic circuit.
摘要翻译：逻辑电路装置包括多个可编程逻辑电路，电路数据存储器，控制单元。多个可编程逻辑电路各自被配置为具有基于电路数据的可变电路部件。每个可编程逻辑电路具有不同的处理性能。电路数据存储器用于存储电路数据的多个电路数据和性能要求。控制单元被配置为选择性地将多个电路数据分配给多个可编程逻辑电路，使得所有可编程逻辑电路的总功率在分配给每个可编程逻辑电路的电路数据的性能要求在处理每个可编程逻辑电路的性能。

92. 发明授权

US07474119B2 Logic circuit apparatus and timeshare operating method of a programmable logic circuit 失效
标题翻译：可编程逻辑电路的逻辑电路设备和分时运行方法
公开(公告)号：US07474119B2
公开(公告)日：2009-01-06
申请号：US10948702
申请日：2004-09-24
申请人： Shinichi Kanno , Yukimasa Miyamoto , Masaya Tarui , Taku Ooneda
发明人： Shinichi Kanno , Yukimasa Miyamoto , Masaya Tarui , Taku Ooneda
IPC分类号： G06F7/38 , H03F19/173
CPC分类号： G06F17/5054
摘要： A logic circuit apparatus that allocates process capability to unit circuits operated in a time divisional manner, including a circuit arrangement information memory which stores circuit arrangement information corresponding to each of plurality of unit circuits, and a programmable logic circuit with a circuit arrangement which can be reconfigured by employing the circuit arrangement information while the programmable logic circuit is being operated, a process data memory which stores both input data and output data related to a process operation of each of the circuits, and a controller which monitors a storage amount of the input data and/or a storage amount of the output data corresponding to each unit circuit, and which controls reconfiguration of the circuit arrangement of the programmable logic circuit when the storage amount satisfies a certain condition.
摘要翻译：一种分时处理能力的逻辑电路装置，包括一个电路布置信息存储器，该电路布置信息存储器存储与多个单元电路中的每一个相对应的电路布置信息，以及一个可编程逻辑电路，该电路布置可以是通过在可编程逻辑电路正在运行时采用电路布置信息来重新配置，存储输入数据和与每个电路的处理操作相关的输出数据的处理数据存储器，以及监视输入的存储量的控制器数据和/或对应于每个单元电路的输出数据的存储量，并且当存储量满足一定条件时，控制可编程逻辑电路的电路装置的重新配置。

93. 发明授权

US07432735B2 Programmable gate array apparatus and method for switching circuits 失效
标题翻译：用于开关电路的可编程门阵列装置和方法
公开(公告)号：US07432735B2
公开(公告)日：2008-10-07
申请号：US11874981
申请日：2007-10-19
申请人： Shinichi Kanno , Toshikatsu Hida
发明人： Shinichi Kanno , Toshikatsu Hida
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17776
摘要： A programmable gate array apparatus includes macrocells connected in series, each macrocell including first group of storage elements in which active context data item is stored and second group of storage elements corresponding to storage elements of first group respectively, in which idle context data item is stored, connects storage elements of second group in series, loads context data item into second group whose storage elements are connected in series, connects first group and second group by connecting storage elements of first group to corresponding storage elements of second group respectively, and swaps context data items between first group and second group.
摘要翻译：可编程门阵列装置包括串联连接的宏小区，每个宏小区包括其中存储有活动上下文数据项的第一组存储单元和对应于第一组存储单元的第二组存储单元，其中存储空闲上下文数据项将第二组的存储元件串联连接，将上下文数据项加载到其存储元件串联连接的第二组中，通过将第一组的存储元件分别连接到第二组的相应存储元件，并将交换上下文第一组与第二组之间的数据项。

94. 发明授权

US07386741B2 Method and apparatus for selectively assigning circuit data to a plurality of programmable logic circuits for maintaining each programmable logic circuit within an operation range at a minimum voltage 有权
标题翻译：用于选择性地将电路数据分配给多个可编程逻辑电路以将每个可编程逻辑电路维持在最小电压的操作范围内的方法和装置
公开(公告)号：US07386741B2
公开(公告)日：2008-06-10
申请号：US11128187
申请日：2005-05-13
申请人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto , Riku Ogawa
发明人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto , Riku Ogawa
IPC分类号： G06F1/00 , G06F1/26
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Programmable logic circuits are changeable circuit components based on circuit data. A circuit data memory stores a plurality of circuit data and performance requirements. A feature data memory stores feature data of each programmable logic circuit. A control unit calculates a minimum voltage of the plurality of programmable logic circuits to execute the plurality of circuit data based on the performance requirements, and selectively assigns the plurality of circuit data to the plurality of programmable logic circuits so that the performance requirement of circuit data assigned to each programmable logic circuit is within the operation range of the programmable logic circuit at the minimum voltage. A supply unit supplies the minimum voltage to the plurality of programmable logic circuits.
摘要翻译：可编程逻辑电路是基于电路数据的可变电路组件。电路数据存储器存储多个电路数据和性能要求。特征数据存储器存储每个可编程逻辑电路的特征数据。控制单元基于性能要求，计算多个可编程逻辑电路的最小电压，以执行多个电路数据，并且选择性地将多个电路数据分配给多个可编程逻辑电路，使得电路数据的性能要求分配给每个可编程逻辑电路的可编程逻辑电路的工作范围内处于最小电压。供电单元向多个可编程逻辑电路提供最小电压。

95. 发明申请

US20080100338A1 LOGIC CIRCUIT APPARATUS 失效
标题翻译：逻辑电路设备
公开(公告)号：US20080100338A1
公开(公告)日：2008-05-01
申请号：US11949072
申请日：2007-12-03
申请人： Taku Ooneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto , Riku Ogawa
发明人： Taku Ooneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto , Riku Ogawa
IPC分类号： H03K19/177
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A logic circuit apparatus includes a plurality of programmable logic circuits, a circuit data memory, a control unit. The plurality of programmable logic circuits are each configured to have a changeable circuit component based on circuit data. Each programmable logic circuit has a different processing performance. The circuit data memory is used to store a plurality of circuit data and performance requirements for the circuit data. The control unit is configured to selectively assign the plurality of circuit data to the plurality of programmable logic circuits so that a total power of all programmable logic circuits minimizes on condition that the performance requirement of the circuit data assigned to each programmable logic circuit is within the processing performance of each programmable logic circuit.
摘要翻译：逻辑电路装置包括多个可编程逻辑电路，电路数据存储器，控制单元。多个可编程逻辑电路各自被配置为具有基于电路数据的可变电路部件。每个可编程逻辑电路具有不同的处理性能。电路数据存储器用于存储电路数据的多个电路数据和性能要求。控制单元被配置为选择性地将多个电路数据分配给多个可编程逻辑电路，使得所有可编程逻辑电路的总功率在分配给每个可编程逻辑电路的电路数据的性能要求在处理每个可编程逻辑电路的性能。

96. 发明申请

US20080016376A1 LOGIC CIRCUIT SYSTEM AND METHOD OF CHANGING OPERATING VOLTAGE OF A PROGRAMMABLE LOGIC CIRCUIT 失效
标题翻译：逻辑电路系统和可编程逻辑电路的工作电压变化方法
公开(公告)号：US20080016376A1
公开(公告)日：2008-01-17
申请号：US11778404
申请日：2007-07-16
申请人： Taku Ooneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
发明人： Taku Ooneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3243 , G06F1/3296 , H03K19/0008 , H03K19/0016 , H03K19/1736 , H03K19/17752 , H03K19/17756 , H03K19/17784 , H03K19/17788 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： A logic circuit system with power consumption that is reduced by automatically varying the clock frequency and operating voltage according to processing capability imposed on programmable logic circuits. The programmable logic circuits are capable of achieving plural circuit functions dynamically and can change realized circuit functions during operation. In addition, the system has a voltage supply portion for supplying a voltage to the programmable logic circuits, a clock signal supply portion for supplying a clock signal to the programmable logic circuits, a change control portion for changing the circuit functions realized by the programmable logic circuits to any one of the circuit functions, an operation time measuring portion for measuring the operation times of the programmable logic circuits to perform processing to achieve the circuit functions, respectively, and a clock-and-voltage determination portion for determining the frequency of the clock signal and the voltage, using the operation times.
摘要翻译：通过根据施加在可编程逻辑电路上的处理能力自动改变时钟频率和工作电压，降低功耗的逻辑电路系统。可编程逻辑电路能够动态地实现多个电路功能，并且可以在操作期间改变实现的电路功能。此外，系统具有用于向可编程逻辑电路提供电压的电压供应部分，用于向可编程逻辑电路提供时钟信号的时钟信号提供部分，用于改变可编程逻辑实现的电路功能的改变控制部分电路中的任何一个电路功能，操作时间测量部分，用于分别测量可编程逻辑电路的运行时间以分别执行处理以实现电路功能;以及时钟和电压确定部分，用于确定时钟信号和电压，使用操作时间。

97. 发明申请

US20070064326A1 Storage medium reproducing apparatus, storage medium reproducing method, and computer program product for reading information from storage medium 失效
标题翻译：存储介质再现装置，存储介质再现方法和用于从存储介质读取信息的计算机程序产品
公开(公告)号：US20070064326A1
公开(公告)日：2007-03-22
申请号：US11360604
申请日：2006-02-24
申请人： Shinichi Kanno
发明人： Shinichi Kanno
IPC分类号： G11B5/09
CPC分类号： G11B20/1833 , G11B20/18 , G11B27/36
摘要： A storage medium reproducing apparatus includes a storage unit, a correction history storage unit, a correction history implementing unit, and a correcting unit. The storage unit includes a plurality of information storage units storing information depending on whether a charge quantity is greater than a predetermined charge quantity threshold value, and a correction code storage unit storing error correction codes for the information stored in the information storage units. The correction history storage unit stores a correction history containing identification information for the information storage unit corrected with an error correction code is performed, and a content of the correction. The correction history implementing unit corrects information in compliance with the content of the correction when the information is read from the information storage unit. The correcting unit performs a correcting operation using an error correction code on the corrected information, and registers the correction history of the corrected information storage unit.
摘要翻译：存储介质再现装置包括存储单元，校正历史存储单元，校正历史实现单元和校正单元。存储单元包括多个信息存储单元，其存储取决于计费量是否大于预定电荷量阈值的信息;以及校正码存储单元，存储存储在信息存储单元中的信息的纠错码。校正历史存储单元存储包含用纠错码校正的信息存储单元的识别信息的校正历史，以及校正的内容。当从信息存储单元读取信息时，校正历史实现单元根据校正的内容校正信息。校正单元使用校正信息上的纠错码执行校正操作，并且登记校正信息存储单元的校正历史。

98. 发明授权

US09331713B2 Encoding apparatus, control method of encoding apparatus, and memory device 有权
标题翻译：编码装置，编码装置的控制方法和存储装置
公开(公告)号：US09331713B2
公开(公告)日：2016-05-03
申请号：US13600929
申请日：2012-08-31
申请人： Yoshiki Saito , Shinichi Kanno , Toshikatsu Hida
发明人： Yoshiki Saito , Shinichi Kanno , Toshikatsu Hida
IPC分类号： H03M13/05 , H03M13/00
CPC分类号： H03M13/05 , H03M13/6516
摘要： According to an embodiment, an encoding apparatus includes a parameter holding unit configured to hold a parameter; an error-detecting code holding unit configured to hold an error-detecting code that is generated from the parameter; an error detecting unit configured to detect an error in the parameter, which is held in the parameter holding unit, with the use of the error-detecting code held in the error-detecting code holding unit; an error correcting unit configured to correct the error detected by the error detecting unit; a selecting unit configured to select the parameter that has been subjected to error correction by the error correcting unit; and an encoding unit configured to encode data with the use of the parameter selected by the selecting unit.
摘要翻译：根据实施例，一种编码装置包括：配置为保存参数的参数保持单元; 错误检测码保持单元，被配置为保存从该参数生成的检错码; 错误检测单元，被配置为使用保持在错误检测码保持单元中的检错码来检测保存在参数保持单元中的参数中的错误; 错误校正单元，被配置为校正由所述错误检测单元检测到的所述错误; 选择单元，被配置为通过误差校正单元选择已经经过纠错的参数; 以及编码单元，被配置为使用由所述选择单元选择的参数来对数据进行编码。

99. 发明授权

US08069394B2 Semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08069394B2
公开(公告)日：2011-11-29
申请号：US13090499
申请日：2011-04-20
申请人： Shinichi Kanno , Hironori Uchikawa
发明人： Shinichi Kanno , Hironori Uchikawa
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
摘要翻译：半导体存储器件包括多个检测码发生器，其被配置为分别产生多个检测码以分别检测多个数据项中的错误;多个第一校正码发生器，被配置为产生多个第一校正码以校正错误在多个第一数据块中，分别包含数据项之一和相应检测码的第一数据块，被配置为生成用于校正第二数据块中的错误的第二校正码的第二校正码发生器，包含第一数据块的第二数据块，以及被配置为非易失性地存储第二数据块，第一校正码和第二校正码的半导体存储器。

100. 发明授权

US07796429B2 Memory controller controlling semiconductor storage device and semiconductor device 失效
公开(公告)号：US07796429B2
公开(公告)日：2010-09-14
申请号：US12039254
申请日：2008-02-28
申请人： Shinichi Kanno , Yosuke Kuroda , Toshio Shirakihara
发明人： Shinichi Kanno , Yosuke Kuroda , Toshio Shirakihara
IPC分类号： G11C16/06
CPC分类号： G11C16/3418
摘要： A memory controller controls a semiconductor storage device including nonvolatile memory cells. The controller includes a generating circuit, and a selection circuit. The generating circuit generates first data based on a second data. The selection circuit retains a cumulative value whose each digit is a cumulative result in each bit of data which is already written in the memory cells. The selection circuit selects one of the first data. A selected first data has a better average of digits in a sum of each bit of the selected first data and each digit of the cumulative value than an unselected first data. The selection circuit retains the sum concerning the selected first data as the new cumulative value.

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