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91. 发明授权

US4962064A Method of planarization of topologies in integrated circuit structures 失效
标题翻译：集成电路结构拓扑的平面化方法
公开(公告)号：US4962064A
公开(公告)日：1990-10-09
申请号：US193478
申请日：1988-05-12
申请人： Jacob D. Haskell , Craig S. Sander , Steven C. Avanzino , Subhash Gupta
发明人： Jacob D. Haskell , Craig S. Sander , Steven C. Avanzino , Subhash Gupta
IPC分类号： H01L21/302 , H01L21/304 , H01L21/3065 , H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/321 , H01L21/76 , H01L21/762
CPC分类号： H01L21/3212 , H01L21/31056 , H01L21/76229 , Y10S148/051 , Y10S438/959
摘要： A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: deposition, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit structure, a conformal oxide layer; depositing a layer of a planarizing material such as polysilicon over the conformal oxide layer; polishing the structure a first time to expose the highest portions of the underlying conformal oxide layer; etching the structure a first time with an etchant system capable of removing the conformal oxide preferentially to the planarizing material; further polishing the structure a second time to remove planarizing material left from the first etching step; and then optionally etching the remainder of the structure to remove any remaining planarizing material and the remaining conformal oxide over the raised portions of the underlying integrated circuit structure to provide the desired highly planarized structure.

92. 发明授权

US06391732B1 Method to form self-aligned, L-shaped sidewall spacers 失效
标题翻译：形成自对准的L形侧壁间隔件的方法
公开(公告)号：US06391732B1
公开(公告)日：2002-05-21
申请号：US09595061
申请日：2000-06-16
申请人： Subhash Gupta , Yelehanka Ramachandramurthy , Vijai Kumar Chhagan
发明人： Subhash Gupta , Yelehanka Ramachandramurthy , Vijai Kumar Chhagan
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/266 , H01L21/31116 , H01L29/6656 , H01L29/7833
摘要： A new method of forming silicon nitride sidewall spacers has been achieved. In addition, a new device profile for a silicon nitride sidewall spacer has been achieved. An isolation region is provided overlying a semiconductor substrate. Polysilicon traces are provided. A liner oxide layer is formed overlying the polysilicon traces and the insulator layer. A silicon nitride layer is formed overlying the liner oxide layer. A polysilicon or amorphous silicon layer is deposited overlying the silicon nitride layer. The polysilicon or amorphous silicon layer is completely oxidized to form a temporary silicon dioxide layer. The temporary silicon dioxide layer is rounded in the corners due to volume expansion during the oxidation step. The temporary silicon dioxide layer is anisotropically etched through to expose horizontal surfaces of the silicon nitride layer while leaving vertical sidewalls of the temporary silicon dioxide layer. The silicon nitride layer is anisotropically etched to form silicon nitride sidewall spacers with an L-shaped profile. The integrated circuit device is completed.
摘要翻译：已经实现了形成氮化硅侧壁间隔物的新方法。此外，已经实现了用于氮化硅侧壁间隔物的新的器件配置。设置在半导体衬底上的隔离区域。提供多晶硅痕迹。在多晶硅迹线和绝缘体层上形成衬里氧化物层。形成覆盖衬垫氧化物层的氮化硅层。沉积氮化硅层上的多晶硅或非晶硅层。多晶硅或非晶硅层被完全氧化以形成临时二氧化硅层。在氧化步骤期间由于体积膨胀，临时二氧化硅层在角部被倒圆。临时二氧化硅层被各向异性地蚀刻以暴露氮化硅层的水平表面，同时留下临时二氧化硅层的垂直侧壁。氮化硅层被各向异性蚀刻以形成具有L形轮廓的氮化硅侧壁间隔物。集成电路装置完成。

93. 发明授权

US6071824A Method and system for patterning to enhance performance of a metal layer of a semiconductor device 失效
标题翻译：用于图案化以提高半导体器件的金属层的性能的方法和系统
公开(公告)号：US6071824A
公开(公告)日：2000-06-06
申请号：US937634
申请日：1997-09-25
申请人： Bhanwar Singh , Subhash Gupta , Mutya Vicente , Susan Hsuching Chen
发明人： Bhanwar Singh , Subhash Gupta , Mutya Vicente , Susan Hsuching Chen
IPC分类号： G03F7/09 , H01L21/027 , H01L21/3213 , H01L21/00
CPC分类号： H01L21/32139 , G03F7/091 , H01L21/0276
摘要： A method and system for patterning a metal layer of a semiconductor device is disclosed. The method and system includes providing a material with an antireflective low dielectric constant hard mask layer (antireflective low k hard mask layer) on top of the metal layer, and providing a photoresist pattern on top of the anti-reflective low k hard mask layer. The method and system further includes etching of the anti-reflective low k hard mask layer and etching of the metal layer, wherein the photoresist is removed but the anti-reflective low k hard mask layer remains. In a preferred embodiment, the mask layer can also be applied at low temperatures (i.e., >300.degree.) to ensure that the physical properties of the integrated circuit are not affected. Finally, the low k material does not have to be removed after processing. Accordingly, through the use of an anti-reflective low k hard mask layer, the metal patterning can be more effectively accomplished in a deep submicron process, particularly a process that is required for 0.18 microns or smaller technologies.
摘要翻译：公开了用于图案化半导体器件的金属层的方法和系统。该方法和系统包括在金属层的顶部提供具有抗反射低介电常数硬掩模层（抗反射低k硬掩模层）的材料，并且在抗反射低k硬掩模层的顶部提供光致抗蚀剂图案。所述方法和系统还包括蚀刻抗反射低k硬掩模层和蚀刻金属层，其中去除光致抗蚀剂，但保留抗反射低k硬掩模层。在优选实施例中，掩模层也可以在低温（即> 300°）下施加，以确保集成电路的物理性质不受影响。最后，低k材料在加工后不必去除。因此，通过使用抗反射低k硬掩模层，可以在深亚微米工艺中更有效地实现金属图案化，特别是0.18微米或更小技术所需的工艺。

94. 发明授权

US5841196A Fluted via formation for superior metal step coverage 失效
标题翻译：通过形成凹槽以获得优异的金属台阶覆盖
公开(公告)号：US5841196A
公开(公告)日：1998-11-24
申请号：US970314
申请日：1997-11-14
申请人： Subhash Gupta , Robert Flores , Michael Ross Stamm , Eric Thomas Sharp , Erich W. E. Denninger , Pamela G. Dye , Joel Samuel Utz , James K. Kai
发明人： Subhash Gupta , Robert Flores , Michael Ross Stamm , Eric Thomas Sharp , Erich W. E. Denninger , Pamela G. Dye , Joel Samuel Utz , James K. Kai
IPC分类号： H01L21/768 , H01L23/522 , H01L21/00
CPC分类号： H01L21/76804 , H01L23/5226 , H01L2924/0002
摘要： A method of forming a via in a interlevel dielectric of a semiconductor device wherein the via has a fluted sidewall. A semiconductor substrate is provided having a first conductive layer formed thereon. A dielectric layer is then formed on the first conductive layer. A photoresist layer is deposited on a dielectric layer and a contact opening is formed in the photoresist layer to expose a contact region of the dielectric layer. A first etch step is performed to remove portions of the dielectric layer proximal to the contact region to form a first stage of the fluted via. The first stage includes a first sidewall stage extending from an upper surface of the dielectric layer at an angle less than 50.degree.. The first stage of the fluted via exterds a first lateral distance which is greater than a lateral dimension of the contact opening. A second etch step is then performed to further remove portions of the dielectric layer to form a second stage of the fluted via. The second stage includes a second sidewall stage extending from the first sidewall stage at a second angle between 40.degree. and 70.degree.. A third etch step is then performed to further remove portions of the dielectric layer to form a third and final. stage of the fluted via. The fluted via extends from an upper surface of the dielectric layer to an upper surface of the first conductive layer. The third stage includes a third stage sidewall extending from said second stage side wall to said upper surface of said first conductive layer at an angle between 60.degree. and 80.degree..
摘要翻译：一种在半导体器件的层间电介质中形成通孔的方法，其中通孔具有带槽纹的侧壁。提供具有形成在其上的第一导电层的半导体衬底。然后在第一导电层上形成电介质层。在介电层上沉积光致抗蚀剂层，并且在光致抗蚀剂层中形成接触开口以暴露电介质层的接触区域。执行第一蚀刻步骤以去除接近接触区域的电介质层的部分，以形成槽纹通孔的第一级。第一级包括从电介质层的上表面以小于50°的角度延伸的第一侧壁级。槽纹通过的第一阶段通过大于接触开口的横向尺寸的第一横向距离。然后执行第二蚀刻步骤以进一步去除介电层的部分以形成槽纹通孔的第二级。第二阶段包括从第一侧壁台以40°至70°之间的第二角度延伸的第二侧壁台。然后执行第三蚀刻步骤以进一步去除介电层的部分以形成第三和最终。槽的通道的阶段。带槽通孔从电介质层的上表面延伸到第一导电层的上表面。第三级包括第三级侧壁，从第二级侧壁延伸至所述第一导电层的上表面，角度为60°至80°。

95. 发明授权

US5814560A Metallization sidewall passivation technology for deep sub-half micrometer IC applications 失效
标题翻译：金属化侧壁钝化技术，用于深半微米IC应用
公开(公告)号：US5814560A
公开(公告)日：1998-09-29
申请号：US564752
申请日：1995-11-29
申请人： Robin W. Cheung , Simon S. Chan , Subhash Gupta
发明人： Robin W. Cheung , Simon S. Chan , Subhash Gupta
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/768 , H01L23/528 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76886 , H01L23/5283 , H01L23/53223 , H01L2924/0002
摘要： A method is provided for forming metal interconnect structures which resists the formation of pile-ups caused by electromigration. Each metal interconnect structure includes an aluminum interconnect sandwiched between two refractory metal layers. The method of the present invention involves forming a layer of aluminum intermetallic alloy on the sidewalls of the aluminum interconnects. The layer of aluminum intermetallic alloy provides reinforcement for the sidewalls. The layer of aluminum intermetallic alloy comprises aluminum-refractory metal alloy. The aluminum-refractory metal alloy is formed by reacting the exposed aluminum on the sidewalls with refractory metal-containing precursor material. After the formation of the layer of aluminum intermetallic alloy the sidewalls of the aluminum interconnects, the formation of pile-ups will be suppressed. Thus, the lifetime of the aluminum interconnects is extended. Accordingly, the method of the present invention improves the reliability and wear resistance of integrated circuits employing aluminum interconnects.
摘要翻译：提供一种用于形成金属互连结构的方法，其抵抗由电迁移引起的堆积的形成。每个金属互连结构包括夹在两个难熔金属层之间的铝互连。本发明的方法包括在铝互连件的侧壁上形成铝金属间合金层。铝金属间合金层为侧壁提供加固。铝金属间合金层包括铝 - 难熔金属合金。铝 - 难熔金属合金是通过将侧壁上暴露的铝与含难熔金属的前体材料反应而形成的。在形成铝金属间合金层之后，铝互连的侧壁，堆积的形成将被抑制。因此，铝互连的寿命延长。因此，本发明的方法提高了采用铝互连的集成电路的可靠性和耐磨性。

96. 发明授权

US5795823A Self aligned via dual damascene 失效
标题翻译：通过双镶嵌自对准
公开(公告)号：US5795823A
公开(公告)日：1998-08-18
申请号：US752807
申请日：1996-11-20
申请人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
发明人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
IPC分类号： H01L21/60 , H01L21/768 , H01L23/522 , H01L21/441
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76877 , H01L21/76897 , H01L23/5226 , H01L2221/1036 , H01L2924/0002
摘要： A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings. The sidewalls serve as self aligned mask for etching via openings. The conformal material is either a conductive material which is left in place after the via openings are formed or an insulating material which is removed. In the former, the partially filled conductive line openings are filled with additional conductive material along with the via, which is either the same or different conductive material. In the latter, the conductive line openings and vias are filled with the same conductive material.
摘要翻译：一种用于集成电路和用于半导体器件的衬底载体的绝缘体分隔开的导线的连接通孔和通孔的方法，其中使用双镶嵌仅具有一个用于形成导电线和通孔的掩模图案。导电线的掩模图案包含在绝缘材料中要形成通孔开口的横向扩大区域。在产生具有横向扩大区域的导电线路开口之后，开口用适形材料填充，其保护材料的蚀刻选择性基本上小于绝缘材料对用于蚀刻绝缘材料的附魔的蚀刻选择性，并且其蚀刻选择性基本上大于绝缘材料到其附魔。保形材料被各向异性地蚀刻以在扩大区域中形成侧壁并且移除侧壁之间的材料，而留下留在导电线开口部分中的材料。侧壁用作通过开口蚀刻的自对准掩模。保形材料是导电材料，其在形成通孔开口之后留在适当位置或者被去除的绝缘材料。在前者中，部分填充的导电线路开口与另外的导电材料一起填充，该通孔是相同或不同的导电材料。在后者中，导电线路开口和通孔用相同的导电材料填充。

97. 发明授权

US5717621A Speedup for solution of systems of linear equations 失效
标题翻译：线性方程组解的加速
公开(公告)号：US5717621A
公开(公告)日：1998-02-10
申请号：US411918
申请日：1995-03-28
申请人： Subhash Gupta , Ravi Mehrotra
发明人： Subhash Gupta , Ravi Mehrotra
IPC分类号： G06F17/12 , G06F7/38
CPC分类号： G06F17/12
摘要： An apparatus and method for solving a system of linear equations uses a sequence of matrix-vector multiplications wherein the matrix to be multiplied is derived from an expansion point matrix that permits rapid convergence. The matrix-vector multiplication form of the sequence permits calculations to be performed on a network of parallel processors.
摘要翻译：用于求解线性方程组的装置和方法使用矩阵向量乘法序列，其中要乘以的矩阵从允许快速收敛的扩展点矩阵导出。序列的矩阵向量乘法形式允许在并行处理器的网络上执行计算。

98. 发明授权

US5705430A Dual damascene with a sacrificial via fill 失效
标题翻译：双镶嵌与牺牲通过填充
公开(公告)号：US5705430A
公开(公告)日：1998-01-06
申请号：US486777
申请日：1995-06-07
申请人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
发明人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76808 , H01L2221/1031
摘要： A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a sacrificial via fill. A first layer of insulating material is formed with via openings. The openings are filled with a sacrificial removable material. A second layer of insulating material is deposed on the first layer. In one embodiment, the etch selectivity to the etchant of the second layer is essentially the same as the sacrificial via fill and, preferably, is substantially higher than second layer. Using a conductive line pattern aligned with the via openings, conductive line openings are etched in the second insulating layer and, during etching, the sacrificial fill is removed from the via openings. In a second embodiment, the sacrificial material is not etchable by the etchant for forming the conductive line openings and, after formation of the conductive line openings, the sacrificial material is removed with an etchant to which the first insulating layer is resistive or less selective. A conductive material now is deposited in the conductive line and via openings.
摘要翻译：一种双镶嵌方法，用于制造用于集成电路的绝缘体分隔开的导电线路的互连电平和用于半导体器件的衬底载体的通孔，其使用牺牲通孔填充物。第一层绝缘材料形成有通孔。开口填充有牺牲可移除材料。在第一层上放置第二层绝缘材料。在一个实施例中，对第二层的蚀刻剂的蚀刻选择性基本上与牺牲通孔填充相同，并且优选地基本上高于第二层。使用与通孔开口对准的导电线图案，在第二绝缘层中蚀刻导电线开口，并且在蚀刻期间，将牺牲填充物从通孔开口移除。在第二实施例中，牺牲材料不可蚀刻用于形成导电线路开口的蚀刻剂，并且在形成导电线路开口之后，用第一绝缘层具有电阻或较小选择性的蚀刻剂去除牺牲材料。导电材料现在沉积在导电线和通孔中。

99. 发明授权

US5691238A Subtractive dual damascene 失效
标题翻译：扣除双镶嵌
公开(公告)号：US5691238A
公开(公告)日：1997-11-25
申请号：US478321
申请日：1995-06-07
申请人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
发明人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
IPC分类号： H01L21/768 , H01L23/522 , H01L21/44
CPC分类号： H01L23/5226 , H01L21/76807 , H01L21/76813 , H01L21/76877 , H01L21/76885 , H01L2924/0002
摘要： A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first used to etch completely through the layer to form conductive line openings. The openings are completely filled with a conductive material and planarized so that the surfaces of the conductive material and the insulating layer are coplanar. A via pattern is aligned perpendicular to the conductive lines and the conductive material is etched half way through the conductive lines in other than the areas covered by the via pattern. The openings thus created in the upper portion of the conductive lines are filled with insulating material to complete the dual damascene interconnection level with the conductive lines in the lower portion of the insulating layer and upwardly projecting vias in the upper portion of the layer. In addition, a triple damascene layer is formed by starting with an insulating layer about one-third thicker than normal and by combining the standard dual damascene method with the above described method. The resulting interconnection level structure comprises conductive lines having upwardly and downwardly projecting vias.
摘要翻译：一种制造导线的互连电平的方法，以及用于集成电路的绝缘和用于半导体器件的衬底载体分离的通孔的方法，其使用反向镶嵌来形成导电线和通孔。首先使用导电线图案来完全蚀刻该层以形成导电线开口。开口完全被导电材料填充并平坦化，使得导电材料和绝缘层的表面是共面的。通孔图案垂直于导电线对齐，并且导电材料被除了通孔图案覆盖的区域之外的一半蚀刻通过导电线。由此在导线的上部形成的开口用绝缘材料填充，以完成与绝缘层的下部中的导电线和层的上部中的向上突出的通孔的双镶嵌互连水平。此外，通过从绝对层开始比正常厚约三分之一的厚度并通过将标准双镶嵌方法与上述方法组合来形成三镶嵌层。所产生的互连级联结构包括具有向上和向下突出的通孔的导线。

100. 发明授权

US5646448A Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device 失效
标题翻译：用于减少与半导体器件中的导电通孔相关的电迁移效应的铜芯片
公开(公告)号：US5646448A
公开(公告)日：1997-07-08
申请号：US699821
申请日：1996-08-19
申请人： Richard K. Klein , Darrell Erb , Steven Avanzino , Robin Cheung , Scott Luning , Bryan Tracy , Subhash Gupta , Ming-Ren Lin
发明人： Richard K. Klein , Darrell Erb , Steven Avanzino , Robin Cheung , Scott Luning , Bryan Tracy , Subhash Gupta , Ming-Ren Lin
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76805 , H01L21/76877 , Y10S257/915 , Y10S438/927
摘要： A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.
摘要翻译：多层半导体结构包括导电通孔。导电通孔包括具有高抗电迁移性的金属颗粒。沉淀物由沉积在通孔上的铜或金的保形层制成，以形成位于通孔中的铜或金储存器或触点。在储存器和绝缘层之间设置阻挡层以防止颗粒扩散到绝缘层中。颗粒可以通过选择性沉积或通过蚀刻保形层形成。可以通过溅射，准直溅射，化学气相沉积（CVD），浸渍，蒸发或其它方式沉积共形层。可以通过各向异性干蚀刻，等离子体辅助蚀刻或其它层去除技术来蚀刻阻挡层和颗粒。

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