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    • 93. 发明申请
    • Method of optimizing pick-to-ship process
    • 优化拣货过程的方法
    • US20050010424A1
    • 2005-01-13
    • US10614761
    • 2003-07-08
    • Marc ShermanJeffrey Smith
    • Marc ShermanJeffrey Smith
    • G06Q10/00G06F17/60
    • G06Q10/087
    • A method, program and system for fulfilling orders is provided by the present invention. The invention includes receiving a product order that specifies product type and quantity and then printing a document that lists the content of the order. An order identification code (i.e. barcode) on the document is input by warehouse personnel. Next a product identification code taken from a physical product is input and compared with the product order. If the product corresponding to the product identification code is part of the order, acquisition of the product is confirmed and it is toward completion of the order. If the product corresponding to the product identification code is not part the order, an error signal is returned. The above steps are repeated until the specified quantity of each product type in the order is entered. An error signal is returned if more than the specified quantity of any product in the order is input. The order is completed and a shipping label is printed only after all products contained in the order have been acquired and entered in the specified quantity.
    • 本发明提供了一种满足订单的方法,程序和系统。 本发明包括接收指定产品类型和数量的产品订单,然后打印列出订单内容的文档。 文件上的订单识别码(即条形码)由仓库人员输入。 接下来,从物理产品中取出的产品标识码被输入并与产品订单进行比较。 如果与产品标识码相对应的产品是订单的一部分,则确认产品的采购,并完成订单。 如果与产品识别代码相对应的产品不是订单的一部分,则返回错误信号。 重复上述步骤,直到输入订单中的每种产品类型的指定数量。 如果输入了多于指定数量的任何产品,则返回错误信号。 订单完成后,只有在订单中包含的所有产品已经以指定数量获得并输入后,才会打印出货标签。
    • 94. 发明授权
    • Microprocessor PLL clock circuit with selectable delayed feedback
    • 具有可选延迟反馈的微处理器PLL时钟电路
    • US5446867A
    • 1995-08-29
    • US890937
    • 1992-05-29
    • Ian YoungKeng L. WongJeffrey Smith
    • Ian YoungKeng L. WongJeffrey Smith
    • G06F1/10H03L7/081H03L7/089G06F1/00G06F1/04G06F1/06
    • H03L7/081G06F1/10H03L7/0891
    • A circuit for use in high performance microprocessor systems which eliminates skew between a clock signal internal to the microprocessor core and inputs generated by a clock signal external to the microprocessor core. The circuit includes a phase locked loop (PLL), a delay line and a clock driver. The PLL locks and deskews the external clock edge to that of the internal clock to thereby provide an overall reduction of the setup and hold time window to satisfy the tight I/O timings required by high performance microprocessor systems. By incorporating the same PLL in all the closely coupled components of the microprocessor core, similar temperature and power supply tracking of such components is achieved. The PLL is a charge-pump based circuit of the type known in the art incorporating a phase detector, charge pump, loop filter and voltage controlled oscillator (VCO). However, the inclusion of the delay line in the feedback path of the PLL provides advantages not available from PLLs without such a delay line. A programmable tap is provided in the delay line which allows the I/O circuitry of the microprocessor to work with either CMOS or TTL input specifications. Specifically, compensation is provided for the differences in propagation delay between CMOS and TTL input buffers.
    • 用于高性能微处理器系统的电路,其消除了微处理器内核内部的时钟信号与由微处理器核心外部的时钟信号产生的输入之间的偏差。 该电路包括锁相环(PLL),延迟线和时钟驱动器。 PLL锁定并将外部时钟边沿撇除为内部时钟的边沿,从而提供建立和保持时间窗口的全面减少,以满足高性能微处理器系统所需的紧密I / O时序。 通过将相同的PLL结合在微处理器核心的所有紧密耦合的组件中,实现了类似的温度和电源跟踪这些组件。 PLL是本领域已知的类型的基于电荷泵的电路,其包括相位检测器,电荷泵,环路滤波器和压控振荡器(VCO)。 然而,在PLL的反馈路径中包括延迟线提供了在没有这样的延迟线的情况下不能从PLL获得的优点。 在延迟线上提供了一个可编程分接头,允许微处理器的I / O电路工作在CMOS或TTL输入规格。 具体来说,为CMOS和TTL输入缓冲器之间的传播延迟的差异提供了补偿。