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91. 外观设计

USD490350S1 Anchor bracket for a disc brake 失效
标题翻译：用于盘式制动器的支架
公开(公告)号：USD490350S1
公开(公告)日：2004-05-25
申请号：US29181591
申请日：2003-05-13
申请人： Peter Blaschke , Lixin Zhang , Mingan Tan
设计人： Peter Blaschke , Lixin Zhang , Mingan Tan

92. 发明授权

US09221838B2 Inhibitors of AKT activity 有权
标题翻译： AKT活性抑制剂
公开(公告)号：US09221838B2
公开(公告)日：2015-12-29
申请号：US13517219
申请日：2010-12-23
申请人： Lixin Zhang , Graham Peter Trevitt , Hugues Miel , Frank Burkamp , Timothy Harrison , Andrew John Wilkinson , Charles-Henry Fabritius
发明人： Lixin Zhang , Graham Peter Trevitt , Hugues Miel , Frank Burkamp , Timothy Harrison , Andrew John Wilkinson , Charles-Henry Fabritius
IPC分类号： C07D498/04 , C07D498/14 , C07D405/04 , C07D471/04
CPC分类号： C07D498/04 , C07D471/04 , C07D498/14
摘要： The invention relates to a series of compounds with particular activity as inhibitors of the serine-threonine kinase AKT. Also provided are pharmaceutical compositions comprising same as well as methods for treating cancer.
摘要翻译：本发明涉及作为丝氨酸 - 苏氨酸激酶AKT抑制剂的特定活性的一系列化合物。还提供了包含其的药物组合物以及用于治疗癌症的方法。

93. 发明申请

US20140256357A1 PROVIDING POINTS OF INTEREST TO USER DEVICES IN VARIABLE ZONES 有权
标题翻译：向可变区域中的用户设备提供兴趣点
公开(公告)号：US20140256357A1
公开(公告)日：2014-09-11
申请号：US13842088
申请日：2013-03-15
申请人： Ray Xiaohang Wang , Farhan Shamsi , Yakov Okshtein , David Singleton , Douglas Alexander Gresham , Alan Newberger , Lixin Zhang
发明人： Ray Xiaohang Wang , Farhan Shamsi , Yakov Okshtein , David Singleton , Douglas Alexander Gresham , Alan Newberger , Lixin Zhang
IPC分类号： H04W4/02
CPC分类号： H04W4/027 , G01C21/00 , G01C21/3679 , H04L67/26 , H04W4/02 , H04W4/021 , H04W4/022 , H04W4/029 , H04W4/20 , H04W4/21
摘要： Receiving point of interest zones and alerts on user devices comprises communicating, by a user computing device to a remote computing device, a request for point of interest data corresponding to points of interest within a proximity of the user device; presenting the received point of interest data; identifying a particular point of interest; and outputting an alert regarding the particular point of interest. Receiving point of interest zones on user devices comprises communicating a request for point of interest data; receiving the point of interest data from the remote network device wherein a size of the point of interest zone is determined based on a density of points of interest in the proximity of the user, and wherein the shape of the point of interest zone is expanded in a direction of travel and contracted in the opposite direction; and presenting the received point of interest data.
摘要翻译：在用户设备上接收兴趣点区域和警报包括由用户计算设备向远程计算设备通知与用户设备附近的兴趣点对应的兴趣点数据的请求; 呈现接收的兴趣点数据; 识别一个特定的兴趣点; 并输出关于特定兴趣点的警报。在用户设备上接收兴趣点区域包括传送关于兴趣点数据的请求; 从所述远程网络设备接收所述兴趣点数据，其中，基于所述用户附近的兴趣点的密度来确定所述兴趣点区域的大小，并且其中所述兴趣点区域的形状在旅行方向与方向相反; 并呈现所接收的兴趣点数据。

94. 发明申请

US20140243342A1 COMPOSITIONS AND METHODS FOR PROPHYLAXIS AND THERAPY FOR MENIERES DISEASE 审中-公开
标题翻译：预防和治疗男性疾病的组合物和方法
公开(公告)号：US20140243342A1
公开(公告)日：2014-08-28
申请号：US14183148
申请日：2014-02-18
申请人： Lixin Zhang
发明人： Lixin Zhang
IPC分类号： A61K31/53 , A61K31/137
CPC分类号： A61K31/53 , A61K31/137 , A61K2300/00
摘要： Provided are articles of manufacture, compositions and methods for prophylaxis and/or therapy for disorders involving dizziness and/or vertigo. The articles of manufacture and compositions contain lamotrigine and/or bupropion and pharmaceutically acceptable salts thereof. The compositions include pharmaceutical compositions which are intended to alleviate dizziness and/or vertigo. In certain aspects the disclosure includes articles of manufacture and kits which include printed material which provides an indication that the articles or compositions are intended to be used for prophylaxis and/or therapy of Meniere's disease or a symptom thereof.
摘要翻译：提供了涉及眩晕和/或眩晕的疾病的预防和/或治疗的制品，组合物和方法。制品和组合物含有拉莫三嗪和/或安非他酮及其药学上可接受的盐。组合物包括旨在减轻眩晕和/或眩晕的药物组合物。在某些方面，本公开包括制品和试剂盒，其包括印刷材料，其提供用于预防和/或治疗梅尼埃病或其症状的制品或组合物的指示。

95. 发明授权

US08783198B2 Spar hull belly strake design and installation method 有权
标题翻译： Spar船体腹部设计和安装方法
公开(公告)号：US08783198B2
公开(公告)日：2014-07-22
申请号：US13147256
申请日：2010-01-28
申请人： Michael Y. H. Luo , Lixin Zhang , Kostas Filoktitis Lambrakos , Vera Mohr
发明人： Michael Y. H. Luo , Harvey O. Mohr , Lixin Zhang , Kostas Filoktitis Lambrakos
IPC分类号： F15D1/10
CPC分类号： B63B1/048 , B63B35/4406 , B63B39/005 , B63B2035/442
摘要： A spar hull for a floating vessel can include a hard tank having a belly portion, a fixed strake coupled to the outer surface of the tank and a folding strake coupled to the belly portion of the tank, the folding strake having one or more strake panels and one or more support frames. A method for installing folding belly strakes on a spar hull may include providing a floating spar hull having a hard tank with a belly side, rotating the spar so that the belly side is in a first workable position, coupling at least one folding strake to the belly side of the spar, and coupling the strake in a folded position for transport. The method may include positioning the spar hull offshore in a transport position, upending the spar hull, unfolding the strake, fixing the strake in the unfolded position and installing the spar hull.
摘要翻译：用于浮动船只的翼梁可以包括具有腹部的硬罐，耦合到罐的外表面的固定板条和耦合到罐的腹部的折叠板，折叠板具有一个或多个板条板和一个或多个支撑框架。用于在翼梁上安装折叠式腹板的方法可以包括：提供具有带有腹部侧面的硬罐的浮动翼梁，旋转翼梁使得腹部侧处于第一可操作位置，将至少一个折叠板连接到翼梁的腹部侧面，并将平台连接在折叠位置以便运输。该方法可以包括将桨叶船体近海定位在运输位置，从而升高翼梁船体，展开船形板，将船板固定在展开位置并安装翼梁船体。

96. 发明申请

US20110283067A1 Target Memory Hierarchy Specification in a Multi-Core Computer Processing System 失效
标题翻译：多核计算机处理系统中的目标内存层次规范
公开(公告)号：US20110283067A1
公开(公告)日：2011-11-17
申请号：US12777603
申请日：2010-05-11
申请人： Tong Chen , Yaoqing Gao , Kevin K. O'Brien , Zehra Sura , Lixin Zhang
发明人： Tong Chen , Yaoqing Gao , Kevin K. O'Brien , Zehra Sura , Lixin Zhang
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0862 , G06F2212/6028
摘要： Target memory hierarchy specification in a multi-core computer processing system is provided including a system for implementing prefetch instructions. The system includes a first core processor, a dedicated cache corresponding to the first core processor, and a second core processor. The second core processor includes instructions for executing a prefetch instruction that specifies a memory location and the dedicated local cache corresponding to the first core processor. Executing the prefetch instruction includes retrieving data from the memory location and storing the retrieved data on the dedicated local cache corresponding to the first core processor.
摘要翻译：提供了多核计算机处理系统中的目标存储器层级规范，包括用于实现预取指令的系统。该系统包括第一核心处理器，对应于第一核心处理器的专用缓存器和第二核心处理器。第二核心处理器包括用于执行指定存储器位置的预取指令和对应于第一核心处理器的专用本地高速缓存的指令。执行预取指令包括从存储器位置检索数据并将检索的数据存储在与第一核心处理器对应的专用本地高速缓存上。

97. 发明授权

US07962722B2 Branch target address cache with hashed indices 有权
标题翻译：具有散列索引的分支目标地址缓存
公开(公告)号：US07962722B2
公开(公告)日：2011-06-14
申请号：US12024219
申请日：2008-02-01
申请人： Sheldon B. Levenstein , David S. Levitan , Lixin Zhang
发明人： Sheldon B. Levenstein , David S. Levitan , Lixin Zhang
IPC分类号： G06F9/32 , G06F9/34
CPC分类号： G06F9/3806 , G06F9/3844
摘要： In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including a branch target address cache (BTAC) including a plurality of entries for storing branch target address predictions. The BTAC includes index logic that selects an entry to access utilizing a BTAC index based upon at least a set of higher order bits of an instruction address and a set of lower order bits of the instruction address.
摘要翻译：在至少一个实施例中，处理器包括至少一个执行单元，其执行耦合到至少一个执行单元的指令和指令排序逻辑，其从存储器系统取出用于由至少一个执行单元执行的指令。指令排序逻辑包括分支目标地址高速缓存（BTAC），其包括用于存储分支目标地址预测的多个条目。 BTAC包括索引逻辑，其基于指令地址的至少一组较高位和指令地址的较低位的集合来选择使用BTAC索引的访问条目。

98. 发明申请

US20110055827A1 Cache Partitioning in Virtualized Environments 有权
标题翻译：虚拟化环境中的高速缓存分区
公开(公告)号：US20110055827A1
公开(公告)日：2011-03-03
申请号：US12546791
申请日：2009-08-25
申请人： Jiang Lin , Lixin Zhang
发明人： Jiang Lin , Lixin Zhang
IPC分类号： G06F12/08 , G06F9/455
CPC分类号： G06F9/455 , G06F12/084 , G06F12/0842 , G06F12/0848 , G06F12/0864 , G06F12/121
摘要： A mechanism is provided in a virtual machine monitor for providing cache partitioning in virtualized environments. The mechanism assigns a virtual identification (ID) to each virtual machine in the virtualized environment. The processing core stores the virtual ID of the virtual machine in a special register. The mechanism also creates an entry for the virtual machine in a partition table. The mechanism may partition a shared cache using a vertical (way) partition and/or a horizontal partition. The entry in the partition table includes a vertical partition control and a horizontal partition control. For each cache access, the virtual machine passes the virtual ID along with the address to the shared cache. If the cache access results in a miss, the shared cache uses the partition table to select a victim cache line for replacement.
摘要翻译：在虚拟机监视器中提供了一种机制，用于在虚拟化环境中提供高速缓存分区。该机制为虚拟化环境中的每个虚拟机分配一个虚拟标识（ID）。处理核心将虚拟机的虚拟ID存储在专用寄存器中。该机制还为分区表中的虚拟机创建一个条目。该机制可以使用垂直（方式）分区和/或水平分区来划分共享高速缓存。分区表中的条目包括垂直分区控制和水平分区控制。对于每个缓存访问，虚拟机将虚拟ID与该地址一起传递到共享缓存。如果缓存访问导致错过，共享缓存使用分区表选择受害缓存行进行替换。

99. 发明授权

US07698508B2 System and method for reducing unnecessary cache operations 失效
标题翻译：减少不必要的缓存操作的系统和方法
公开(公告)号：US07698508B2
公开(公告)日：2010-04-13
申请号：US11674960
申请日：2007-02-14
申请人： Ramakrishnan Rajamony , Hazim Shafi , William Evan Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , Hazim Shafi , William Evan Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/0817
摘要： A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.
摘要翻译：一种用于数据处理系统中缓存管理的系统和方法。数据处理系统包括处理器和存储器层级。存储器层级至少包括上部存储器高速缓存，至少下部存储器高速缓存和回写数据结构。响应于从上部存储器高速缓存替换数据，上部存储器高速缓存检查回写数据结构以确定数据是否存在于下部存储器高速缓存中。如果数据存在于较低存储器高速缓存中，则数据将在上部存储器高速缓存中替换，而不会将数据丢弃到较低的内存高速缓存。

100. 发明申请

US20090288063A1 PREDICATION SUPPORTING CODE GENERATION BY INDICATING PATH ASSOCIATIONS OF SYMMETRICALLY PLACED WRITE INSTRUCTIONS 有权
标题翻译：通过表示对称写入指令的路径协会来确定支持代码生成
公开(公告)号：US20090288063A1
公开(公告)日：2009-11-19
申请号：US12123083
申请日：2008-05-19
申请人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
发明人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
IPC分类号： G06F9/44
CPC分类号： G06F8/4451
摘要： A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.
摘要翻译：用于无序指令处理的预测技术提供了低硬件开销的有效的无序执行。一个特殊的操作代码区分了程序代码的统一区域，其中包含依赖于条件分辨率的预测指令。与特殊操作码相关联的字段或操作数指示操作码后面的指令数，并且还包含每个指令与其对应条件路径的关联的指示。区域中的每个条件寄存器写入对于每个条件路径都有相应的寄存器写入，如果对称性尚未存在，编译器插入附加的寄存器写入，形成一组寄存器写操作。因此，统一的指令流可以使用与相同重名资源相关联的寄存器写入进行解码和分派，并且通过执行由解析条件指定的特定指令来解决条件寄存器写入。

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