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91. 发明授权

US06991443B2 Oil injected screw compressor 有权
标题翻译：注油螺杆压缩机
公开(公告)号：US06991443B2
公开(公告)日：2006-01-31
申请号：US10775193
申请日：2004-02-11
申请人： Masakazu Aoki , Masahiko Takano , Masaaki Toda
发明人： Masakazu Aoki , Masahiko Takano , Masaaki Toda
IPC分类号： F01C1/16 , F03C2/00
CPC分类号： F01C21/007 , F04C29/026 , Y10S55/17 , Y10S418/01
摘要： An oil injected screw compressor has an oil separating mechanism integrated with a compressor and hence is made compact in size. A male rotor and a female rotor are received in a rotor casing. The shafts of these rotors are arranged substantially in a horizontal direction. An inner cylindrical wall is arranged under the rotor casing with its center axis arranged substantially in a vertical direction and an outer wall is arranged substantially in a concentric position with the inner wall. A lower casing is hermetically joined to the outer wall. Oil in the working gas which is injected in the compression process of the oil injected screw compressor is primarily separated from the working gas between the inner wall and the outer wall. The primarily separated working gas flows up inside the inner wall and is guided through a manifold into an oil separating element case where the oil is secondarily separated from the working gas.
摘要翻译：注油螺杆式压缩机具有与压缩机一体化的油分离机构，因此尺寸紧凑。阳转子和母转子接收在转子壳体中。这些转子的轴基本上在水平方向上布置。内圆柱形壁布置在转子壳体的下方，其中心轴基本上沿垂直方向布置，并且外壁基本上与内壁基本上处于同心位置。下壳体气密地连接到外壁。在注油螺杆压缩机的压缩过程中注入的工作气体中的油主要与内壁和外壁之间的工作气体分离。主要分离的工作气体在内壁内流动，并通过歧管被引导到油分离元件壳体中，其中油与工作气体二次分离。

92. 发明授权

US06970019B2 Semiconductor integrated circuit device having power reduction mechanism 失效
标题翻译：具有功率降低机构的半导体集成电路装置
公开(公告)号：US06970019B2
公开(公告)日：2005-11-29
申请号：US10704849
申请日：2003-11-12
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： G11C5/00 , H01L27/02 , H03K3/356 , H03K19/00 , H03K19/0185 , H03K19/094 , H03K19/0948 , H03K19/096 , H03K19/20
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H01L27/0218 , H03K3/356113 , H03K19/0013 , H03K19/0016 , H03K19/01721
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with MOS transistors. The semiconductor integrated circuit device includes a current control device. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors, that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译：半导体集成电路器件由各自提供有MOS晶体管的逻辑门组成。半导体集成电路装置包括电流控制装置。该电路可用于在具有操作模式和用于功率降低的低功率备用或睡眠模式的高功耗模式和低功耗模式之间运行的设备中，例如微处理器。

93. 发明授权

US06909647B2 Semiconductor device having redundancy circuit 失效
标题翻译：具有冗余电路的半导体器件
公开(公告)号：US06909647B2
公开(公告)日：2005-06-21
申请号：US10813240
申请日：2004-03-31
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C5/00 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
摘要翻译：半导体存储器具有冗余电路的缺陷恢复方案。存储器中的存储器阵列具有多个字线，多个位线，备用位线和多个存储器单元。冗余电路包括具有可编程元件的一个或多个比较电路，其作为用于在其中存储存在于存储器阵列中的缺陷地址的存储器。冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。冗余电路的每个比较电路将在其中输入的信息（数据），例如可能在地址多路复用系统的控制下的列和行地址与在比较电路的可编程元件中编程的信息（数据）进行比较。在此比较的基础上，进行适当的缺陷恢复。

94. 发明授权

US06894944B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06894944B2
公开(公告)日：2005-05-17
申请号：US10602684
申请日：2003-06-25
申请人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
发明人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
IPC分类号： H01L21/8247 , G11C16/04 , G11C29/00 , G11C29/04 , G11C29/12 , G11C29/42 , H01L21/66 , H01L23/532 , H01L23/544 , H01L27/02 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792 , G11C8/00
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.
摘要翻译：为了降低具有多层布线和铜布线的半导体集成电路中的缺陷冗余和修整的成本，通过使用构成浮动电极的非易失性存储元件，通过第一（第二）存储来存储半导体中存储单元阵列的缺陷的地址多晶硅层或非易失性存储元件被编程用于测试半导体集成电路。结果，在形成非易失性存储元件中不需要特殊的处理。换句话说，非易失性存储元件可以在形成CMOS器件的过程中形成，并且不需要用于编程的激光束的装置，因为在测试中执行编程。因此，可以缩短编程所需的时间，因此可以降低测试成本。

95. 发明授权

US06674117B2 Semiconductor element and semiconductor memory device using the same 失效
公开(公告)号：US06674117B2
公开(公告)日：2004-01-06
申请号：US09915588
申请日：2001-07-27
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L2976
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

96. 外观设计

USD478345S1 Toner cartridge 失效
公开(公告)号：USD478345S1
公开(公告)日：2003-08-12
申请号：US29171297
申请日：2002-11-20
申请人： Hironobu Kinoshita , Naoki Yamaguchi , Masakazu Aoki
设计人： Hironobu Kinoshita , Naoki Yamaguchi , Masakazu Aoki

97. 发明授权

US06577544B2 Semiconductor device having redundancy circuit 失效
标题翻译：具有冗余电路的半导体器件
公开(公告)号：US06577544B2
公开(公告)日：2003-06-10
申请号：US09992001
申请日：2001-11-26
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C700
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
摘要翻译：半导体存储器具有冗余电路的缺陷恢复方案。存储器中的存储器阵列具有多个字线，多个位线，备用位线和多个存储器单元。冗余电路包括具有可编程元件的一个或多个比较电路，其作为用于在其中存储存在于存储器阵列中的缺陷地址的存储器。冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。冗余电路的每个比较电路将在其中输入的信息（数据），例如可能在地址多路复用系统的控制下的列和行地址与在比较电路的可编程元件中编程的信息（数据）进行比较。在此比较的基础上，进行适当的缺陷恢复。

98. 发明授权

US06356119B2 Semiconductor integrated circuit device having power reduction mechanism 失效
公开(公告)号：US06356119B2
公开(公告)日：2002-03-12
申请号：US09766979
申请日：2001-01-23
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： H03K19094
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H01L27/0218 , H03K3/356113 , H03K19/0013 , H03K19/0016 , H03K19/01721
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

99. 发明授权

US06291852B1 Semiconductor element and semiconductor memory device using the same 失效
标题翻译：半导体元件和使用其的半导体存储器件
公开(公告)号：US06291852B1
公开(公告)日：2001-09-18
申请号：US09521970
申请日：2000-03-09
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L2976
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A field-effect semiconductor element implemented with a reduced number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature. In accordance with one embodiment, a carrier confinement region, isolated from a channel and a gate of the semiconductor FET element, is provided to operate as a storage node for trapping the carrier or carriers.
摘要翻译：一种场效应半导体元件，其具有减少的元件数量和减少的面积，并且能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。根据一个实施例，提供了从沟道隔离的载流子限制区域和半导体FET元件的栅极，以用作捕获载体或载流子的存储节点。

100. 发明授权

US06287083B1 Compressed air production facility 有权
标题翻译：压缩空气生产设备
公开(公告)号：US06287083B1
公开(公告)日：2001-09-11
申请号：US09526564
申请日：2000-03-16
申请人： Masakazu Hase , Masakazu Aoki , Hiroyuki Matsuda
发明人： Masakazu Hase , Masakazu Aoki , Hiroyuki Matsuda
IPC分类号： F04B4900
CPC分类号： F04B41/06 , F04B49/025 , F04B2203/0209 , F04B2205/171
摘要： A compressed air production facility includes at least one variable speed compressor and a plurality of constant speed compressor, which are connected in parallel with one another. The variable speed compressor and the plurality of constant speed compressors are capacitively controlled with the use of a pressure in an air reservoir into which discharge air from these compressor are led. Both upper limit pressure at which the variable speed compressor is turned into its load operation mode into its unload operation mode and a lower limit pressure at which the variable speed compressor is turned into its unload operation mode into its load operation mode are set between an upper limit change-over pressure at which all of the plurality of constant speed compressors are turned into their load operation into their unload operation and a lower limit change-over pressure at which all of the plurality of constant speed compressors are changed over from their unload operation into their load operation. With this arrangement, it is possible to provide a power consumption characteristic which is substantially proportional to an air consumption.
摘要翻译：压缩空气生产设备包括彼此并联连接的至少一个变速压缩机和多个恒速压缩机。变速压缩机和多个恒速压缩机通过使用来自这些压缩机的排放空气被引导到的储气器中的压力进行电容性控制。将变速压缩机的负荷运转模式的上限压力设定为卸载运转模式，将变速压缩机变为卸载运转模式的下限压力设定为上部压力所有多个恒速压缩机的所有多个恒速压缩机的负载运转转换为其卸载运转的极限转换压力以及多个恒速压缩机全部从其卸载运转转换的下限转换压力进入其加载操作。通过这种布置，可以提供基本上与空气消耗成正比的功耗特性。

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